Patent information in a large electrical company, exemplified by the situation at Siemens

The special situation of patent information is dealt with against the background of the general problems of information provision. The role of the Patent Department of Siemens as a user of patent information and in the distribution of patent information within the company is discussed. Finally, the present system of current patent information on granted patents and first publications is outlined and an outlook on future developments given.     

Design aspects of MOS-controlled thyristor elements: technology,simulation, and experimental results

2.5-kV thyristor devices have been fabricated with integrated MOS controlled n⁺-emitter shorts and a bipolar turn-on gate using a p-channel DMOS technology. Square-cell geometries with pitch variations ranging from 15 to 30 μm were implemented in one- and two-dimensional arrays with up to 20000 units. The impact of the cell pitch on the turn-off performance and the on-state voltage was studied for arrays with constant cathode area as well as for single-cell structures. By realizing MOS components with submicrometer channel lengths, scaled single cells are shown to turn off with current densities of several kiloamperes per square centimeter at a gate bias of 5 V. In the case of multi-cell ensembles, turn-off performance is limited due to inhomogeneous current distribution. Critical process parameters as well as the device behavior were optimized through multidimensional numerical simulation     

功率器件、电路和系统用的计算机辅助设计技术的进展

最近10年,计算机辅助设计技术(TCAD)的应用已在工业界和学术界普及。计算机硬件和软件迅猛发展和数值算法用的物理模型的精度、速度和鲁棒性显著提高,使TCAD作为晶片加工和计量的补充实验方法,成为降低成本的有效技术。     

Verification of CDM circuit simulation using an ESD evaluation circuit

In this work, the capability of circuit simulation to predict CDM robustness of integrated circuits and to determine weak circuit elements is studied. The applicability is demonstrated for an ESD evaluation circuit designed to enable the analysis and optimization of ESD protection strategies in an early design phase during the introduction of a new technology. CDM circuit simulation is compared to the measurement results of variations of this circuit in two different package types. Failure locations are verified with physical failure analysis. The failure locations and CDM failure levels were reproduced accurately with circuit simulation for all circuit and package variations.     

Design and verification of a stack processor virtual component

Hardware and software codesign and flexibility requirements often necessitate embedded application-specific instruction-set processors in system-on-chip designs. Spaceman, a reusable stack-processor virtual component, offers a customer-configurable instruction set; parameterizable bus widths, stack depths, and stack access ranges; and selectable bus interfaces     

Modeling secondary electron images for linewidth measurement by critical dimension scanning electron microscopy

Modeling of critical dimensions scanning electron microscopy with sub-nanometer uncertainty is required to provide a metrics and to avoid yield loss in the processing of advanced CMOS technologies. In this paper, a new approach is proposed, which includes a new Monte Carlo scheme, a new Monte Carlo code, as well as the coupling with electrostatic fields to take into account self-charging effects.     

A low-power transmission-gate-based 16-bit multiplier for digital hearing aids

The most widespread 16-bit multiplier architectures are compared in terms of area occupation, dissipated energy, and EDP (Energy-Delay Product) in view of low-power low-voltage signal processing for digital hearing aids and similar applications. Transistor-level simulations including back-annotated wire parasitics confirm that the propagation of glitches along uneven and re-convergent paths results in large unproductive node activity. Because of their shorter full-adder chains, Wallace-tree multipliers indeed dissipate less energy than the carry-save (CSM) and other traditional array multipliers (6.0 µW/MHz versus 10.9 µW/MHz and more for 0.25 µm CMOS technology at 0.75 V). By combining the Wallace-tree architecture with transmission gates (TGs), a new approach is proposed to improve the energy efficiency further (3.1 µW/MHz), beyond recently published low-power architectures. Besides the reduction of the overall capacitance, minimum-sized transmission gate full-adders act as RC-low-pass filters that attenuate undesired switching. Finally, minimum size TGs increase the V _dd to ground resistance, hence decreasing leakage dissipation (0.55 nW versus 0.84 nW in CSM and 0.94 nW in Wallace).     

VLSI implementation of MIMO detection using the sphere decoding algorithm

Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high-rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The first ASIC attains maximum-likelihood performance with an average throughput of 73 Mb/s at a signal-to-noise ratio (SNR) of 20 dB; the second ASIC shows only a negligible bit-error-rate degradation and achieves a throughput of 170 Mb/s at the same SNR. The three key contributing factors to high throughput and low complexity are: depth-first tree traversal with radius reduction, implemented in a one-node-per-cycle architecture, the use of the /spl lscr//sup /spl infin//-instead of /spl lscr//sup 2/-norm, and, finally, the efficient implementation of the enumeration approach recently proposed in . The resulting ASICs currently rank among the fastest reported MIMO detector implementations.     

Assessment of the Analytical Capabilities of Scanning Capacitance and Scanning Spreading Resistance Microscopy Applied to Semiconductor Devices

In this work we compare the performance of Scanning Capacitance Microscopy and Scanning Spreading Resistance Microscopy for the characterization of doping profiles in semiconductor devices. Particular attention is devoted to parameters of paramount importance for the failure analysis and the characterization of silicon devices, like the quantitative one-dimensional profiling accuracy, the electrical junction delineation and the two-dimensional sub-micron imaging capability.