Background memory area estimation for multidimensional signalprocessing systems

Memory cost is responsible for a large amount of the chip and/or board area of customized video and image processing system realizations. In this paper, we present a novel technique-founded on data-flow analysis which allows one to address the problem of background memory size evaluation for a given nonprocedural algorithm specification, operating on multidimensional signals with affine indexes. Most of the target applications are characterized by a huge number of signals, so a new polyhedral data-flow model operating on groups of scalar signals is proposed. These groups are obtained by a novel analytical partitioning technique, allowing to select a desired granularity, depending on the application complexity. The method incorporates a way to tradeoff memory size with computational and controller complexity     

Axiom-based ontology matching

Abstract: Managing multiple ontologies is now a core question in most of the applications that require semantic interoperability. The semantic web is surely the most significant application of this report: the current challenge is not to design, develop and deploy domain ontologies but to define semantic correspondences among multiple ontologies covering overlapping domains. In this paper, we introduce a new approach of ontology matching named axiom-based ontology matching. As this approach is founded on the use of axioms, it is mainly dedicated to heavyweight ontologies, but it can also be applied to lightweight ontologies as a complementary approach to the current techniques based on the analysis of natural language expressions, instances and/or taxonomical structures of ontologies. This new matching paradigm is defined in the context of the conceptual graphs model, where the projection (i.e. the main operator for reasoning with conceptual graphs which corresponds to homomorphism of graphs) is used as a means to semantically match the concepts and the relations of two ontologies through the explicit representation of the axioms in terms of conceptual graphs. We also introduce an ontology of representation, called MetaOCGL, dedicated to the reasoning of heavyweight ontologies at the meta-level.     

A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck

Memory latency has always been a major issue in embedded systems that execute memory-intensive applications. This is even more true as the gap between processor and memory speed continues to grow. Hardware and software prefetching have been shown to be effective in tolerating the large memory latencies inherit in large off-chip memories; however, both types of prefetching have their shortcomings. Hardware schemes are more complex and require extra circuitry to compute data access strides, while software schemes generate prefetch instructions, which if not computed carefully may hamper performance. On the other hand, some applications domains (such as multimedia) have a uniform and known a priori memory access pattern, that if exploited, could yield significant application performance improvement. With this characteristic in mind, we present our findings on hiding memory latency using the direct memory access (DMA) mode, which is present in all modern systems, combined with a software prefetch mechanism, and a customized on-chip memory hierarchy mapping. Compared to previous approaches, we are able to estimate the performance and power metrics, without actually implementing the embedded system. Experimental results on nine well known multimedia and imaging applications prove the efficiency of our technique. Finally, we verify the performance estimations by implementing and simulating the algorithms on the TI C6201 processor.     

Efficient system-level functional verification methodology for multimedia applications

Multimedia application design exploration should begin at the system level, to meet low-power and minimum-area requirements. Existing validation techniques mainly concentrate on lower abstraction levels. This system-level methodology combines formal verification of loop-oriented transformations with correctness verification of arithmetic constructs and related control flows. A videoconferencing-decoder example illustrates the methodology's efficiency.     

Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management

MATISSE is a design environment intended for developing systems characterized by a tight interaction between control and data-flow behavior, intensive data storage and transfer, and stringent real-time requirements. Matisse bridges the gap from a system specification, using a concurrent object-oriented language, to an optimized embedded single-chip hardware/software implementation. Matisse supports stepwise exploration and refinement of dynamic memory management, memory architecture exploration, and gradual incorporation of timing constraints before going to traditional tools for hardware synthesis, software compilation, and inter-processor communication synthesis. With this approach, specifications of embedded systems can be written in a high-level programming language using data abstraction. Application of MATISSE on telecom protocol processing systems in the ATM area shows significant improvements in area usage and power consumption.     

Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer

The flexibility and programmability of SDR come at the expense of reduced efficiency and increased energy consumption. This is usually considered as the penalty of SDR. However, the flexibility and programmability have great potentials for improving the system-wide efficiency if they are properly exploited. In this paper, we present a HSDPA chip equalizer that is explicitly designed for SDR implementations. The first SDR-specific feature of our work is the multi-mode operation based on heterogeneous algorithms. The proposed equalizer combines an optimized LMS variant (with subspace-aware extension) and an optimized SRI-RLS algorithm based on QRD. Instead of always applying the powerful SRI-RLS algorithm, the equalizer switches to simple LMS-variant when possible. With negligible BER degradation, the multi-mode operation can reduce 60% of the cycle-count on TI TMS320C6713 for 3GPP case 4 with 16QAM modulation. The proposed equalizer framework also incorporates a generic, robust and efficient scheme for equalization-length adaptation. The length-adaptation scheme can make very fast run-time decision based on an efficient policy-template, which is optimized with large training set at design time. We test 14 representative channel profiles specified in ITU-R M.1225, 3GPP TR 25.943 and 3GPP TS 25.101. Comparing to worst-case based design the length-adaptation achieves more than 10× cycle-count reductions for ten of the cases.     

Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments

In the context of future dynamic applications, systems will exhibit unpredictably varying platform resource requirements. To deal with this, they will not only need to be programmable in terms of instruction set processors, but also at least partial reconfigurability will be required. In this context, it is important for applications to optimally exploit the memory hierarchy under varying memory availability. This article presents a mapping strategy for wavelet-based applications: depending on the encountered conditions, it switches to different memory optimized instantations or localizations, permitting up to 51% energy gains in memory accesses. Systematic and parameterized mapping guidelines indicate which localization should be selected when, for varying algorithmic wavelet parameters. The results have been formalized and generalized to be applicable to more general wavelet-based applications.     

Green Reconfigurable Radio Systems

The wireless standards scene and its evolution strengthens the need for functional flexibility in future radios. Multimode terminals supporting an increasingly large variety of standards (cellular, WLANs, WMANs, WPANs) are subject to a cost increase that is addressed by more flexible radio interfaces. Energy efficiency, however, is the main obstacle to successfully deploying such reconfigurable radios. To address this, it is essential to design energy-scalable SDRs, both for the radio front-end and the digital baseband platform. Complementing this, an essential ingredient is an intelligent controller that optimally exploits this scalability and the run-time dynamics to translate potential energy scalability to actual low-power operation. To realize this goal, an energy-aware cross-layer radio management framework is introduced. It was instantiated in different case studies, showing the applicability of this approach in realistic setups. Results have shown that substantial gains can be achieved through effective cross-layer optimization and problem partitioning. Next, it was shown that SDRs will play a crucial role in enabling CRs, which will enable saving on both the scarce radio spectrum and battery lifetime. A key building block for the design of such CRs, i.e., the appropriate control intelligence to make the SDR platform cognitive, can be derived by incrementally building on the proposed framework. As a result, green (or environment friendly) reconfigurable radio systems will emerge, which offer a wide variety and ubiquitous availability of wireless services, while overcoming energy and spectrum scarcity     

Energy Aware Signal Processing for Software Defined Radio Baseband Implementation

The fast pacing diversity and evolution of wireless communications require a wide variety of baseband implementations within a short time-to-market. Besides, the exponentially increased design complexity and design cost of deep sub-micron silicon highly desire the designs to be reused as much as possible. This yields an increasing demand for reconfigurable/ programmable baseband solutions. Implementing all baseband functionalities on programmable architectures, as foreseen in the tier-2 SDR, will become necessary in the future. However, the energy efficiency of SDR baseband platforms is a major concern. This brings a challenging gap that is continuously broadened by the exploding baseband complexity. We advocate a system level approach to bridge the gap. Specifically, we fully leverage the advantages (programmability) of SDR platforms to compensate its disadvantages (energy efficiency). Highly flexible and dynamic baseband signal processing algorithms are designed and implemented to exploit the abundant dynamics in the environment and the user requirement. Instead of always performing the best effort, the baseband can dynamically and autonomously adjust its work load to optimize the average energy consumption. In this paper, we will introduce such baseband signal processing techniques optimized for SDR implementations. The methodology and design steps will be presented together with 3 representative case studies in HSDPA, WiMAX and 3GPP LTE.