A Totally Self-Checking 1-out-of-3 Code Error Indicator

In this paper, an asynchronous TSC 1-out-of-3 (1/3) code error indicator is introduced that memorizes erroneous 1/3 code inputs 000, 011, 101, 110, 111 with time duration greater than a discrimination time T. Such an error indicator is used to discriminate transient erroneous 1/3 code inputs from real ones as well as to detect faults that cause logical errors and delay faults (short or long) altering the circuit delay outside its specified limits (upper or lower bounds) without causing logical errors. To our knowledge, this error indicator is the first TSC 1/3 code error indicator proposed in the open literature.     

Single error correcting and multiple unidirectional error detecting cyclic an arithmetic codes

We present cyclic AN arithmetic codes capable of single error correction and multiple unidirectional error detection. These codes can be used throughout a fault-tolerant computer, and they eliminate the need for encoding/decoding circuits and code translation circuits. We use criteria for the determination of the unidirectional error detection capability for a given AN code, and we present a new error correction/detection scheme.     

Negative failsafe sequential circuits

The letter presents a new method of designing failsafe sequential circuits by using appropriate negative forms for the next state functions and a proper state assignment of a k-out-of-n code. The use of negative monotone functions makes the circuit oscillate between two states which are outside the normal states of the circuit when the circuit, by any reason, assumes some state outside the normal ones.     

Concurrent Delay Testing in Totally Self-Checking Systems

Prompt detection of even small delay faults, sometimes before causing critical paths to fail, gains importance since stricter test quality requirements for high performance and high density VLSI circuits have to be satisfied in critical applications. This can be achieved by using concurrent delay testing.In this paper a novel idea for concurrent detection of two-rail path delay faults is introduced. It is shown that TSC two-rail code error indicators that monitor pairs of paths with similar propagation delays can be used for concurrent delay testing. Our technique is applied to TSC two-rail code checkers as well as to duplication systems which are the most widely used TSC systems. The design of TSC two-rail code checkers and TSC duplication systems with respect to two-rail path delay faults is achieved for first time in the open literature.