A 14-ns 14-Mb CMOS DRAM with 300-mW active power

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-μm L_eff CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm×6.38-mm chip, organized as either 512 K word×8 b or 1 M word×4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V_cc and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V_cc to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time     

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ

This paper describes a 256 Mb DRAM chip architecture which provides up to ×32 wide organization. In order to minimize the die size, three new techniques: an exchangeable hierarchical data line structure, an irregular sense amp layout, and a split address bus with local redrive scheme in the both-ends DQ were introduced. A chip has been developed based on the architecture with 0.25 μm CMOS technology. The chip measures 13.25 mm×21.55 mm, which is the smallest 256 Mb DRAM ever reported. A row address strobe (RAS) access time of 26 ns was obtained under 2.8 V power supply and 85°C. In addition, a 100 MHz×32 page mode operation, namely 400 M byte/s data rate, in the standard extended data output (EDO) cycle has been successfully demonstrated     

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Describes a 1-Mbit high-speed DRAM (HSDRAM), which has a nominal random access time of less than 27 ns and a column access time of 12 ns with address multiplexing. A double-polysilicon double-metal CMOS technology having PMOS arrays inside n-wells was developed with an average 1.3- mu m feature size. The chip has also been fabricated in a 0.9*shrunken version with an area of 67 mm/sup 2/, showing a 22-ns access time. The chip power consumption is lower than 500 mW at 60-ns cycle time. This HSDRAM, which provides SRAM-like speed while retaining DRAM-like density, allows DRAMs to be used in a broad new range of applications.<>     

An 800-MHz embedded DRAM with a concurrent refresh mode

An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. A concurrent refresh mode is designed to improve the memory utilization to over 99% for a 64 /spl mu/s data retention time. A concurrent refresh scheduler utilizes up-count and down-count registers to identify at least one array to be refreshed at every clock cycle, emulating a classical distributed refresh mode. A command multiplier employs low frequency phased clock signals to generate the clock, commands, and addresses at rates up to 4/spl times/ that of the tester frequency. The macro integrates masked redundancy allocation logic during at speed multibank test. The hardware results show a 312-MHz random access frequency and 800-MHz multibank frequency at 1.2 V, respectively.     

Fault-tolerant designs for 256 Mb DRAM

This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm² 256 Mb DRAM with x32 both-ends DQ. The 256 Mb DRAM consists of sixteen 16 Mb units, each containing one 128 Kb row redundancy block. This row redundancy block architecture allows flexible row redundancy replacement, where random faults, clustered faults, and grouped faults can be efficiently repaired. Flexible column redundancy replacement with interchangeable master DQ's (MDQ) is used to allow a 256 b data compression without causing a data conflict, while improving the column access speed by 2 ns. A depletion NMOS bitline-precharge-current-limiter suppresses the current flow which occurs as a result of a wordline-bitline short-circuit to only 15 μA per cross fail, avoiding a standby current fail. Consequently, the hardware results show a significant yield enhancement of 16 times relative to the intra-block/segment replacement. Detailed simulation results show that this 256 Mb DRAM allows 275 random faults to be repaired with 5.5% silicon area overhead for 80% chip yield     

A 220-mm2, four- and eight-bank, 256-Mb SDRAM withsingle-sided stitched WL architecture

A 220-mm², 256-Mb SDRAM has been fabricated in fully planarized 0.22-μm CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-μm WL pitch in limited space. An intraunit address increment pipeline scheme having two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single ended read-write-drive bus reduce the ICC₄ current to ~90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns. This design also uses a selectable row domain and divided column redundancy scheme that repairs up to ~1400 faults/chip with only 8% chip overhead     

A 7F2 cell and bitline architecture featuring tiltedarray devices and penalty-free vertical BL twists for 4-Gb DRAMs

A 7F² DRAM trench cell and corresponding vertically folded bitline (BL) architecture has been fabricated using a 0.175 μm technology. This concept features an advanced 30° tilted array device layout and an area penalty-free inter-BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals. A significant improvement of signal margin was measured on a 32-Mbyte test chip     

Flexible test mode approach for 256-Mb DRAM

This paper describes a flexible test mode approach developed for a 256-Mb dynamic random access memory (DRAM). Test mode flexibility is achieved by breaking down complicated test mode control into more than one primitive test mode. The primitive test modes can be selected together through a WE CAS Before RAS (WCBR) cycle with a series of addresses for mode select. Although each primitive test mode may not complete a meaningful task alone, their combination performs many complex and powerful test modes. In this design, 64 primitive test modes are available. These can be combined to realize more than 19000 useful test modes. A new signal margin test mode is introduced which allows an accurate signal margin test even for small capacitance cells, which are difficult to identify in existing plate-bump method. A flexible multiwordline select test mode effectively performs a toggled wordline disturb test, a long t_RAS wordline disturb test, and a transfer gate stress voltage test, without causing any unnatural array disturbance. Finally, test modes, which can directly control the timing of sense amplifiers and column select lines, are discussed     

A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitlinearchitecture

A 390-mm², 16-bank, 1-Gb, double-data-rate (DDR) synchronous dynamic random access memory (SDRAM) has been fabricated in fully planarized 0.175-μm, 8F² trench cell technology. The 1-Gb SDRAM employs a hybrid bitline architecture with 512 cells/local-bitline (LBL). Four LBL pairs are connected through multiplexers to each sense amplifier (SA). Two of the LBL pairs are coupled to the SA by wiring over two other LBL pairs using hierarchical bitlines. This results in a reduction of the number of the SA's to 1/4, reducing the chip size by 6%. A hierarchical column-select-line scheme is incorporated with a hierarchical dataline (MDQ) architecture. This makes 16-bank organization possible while sharing hierarchical column decoders and second sense amplifiers. A hierarchical 8-b prefetch scheme employs four MDQ's for each read-write drive (RWD) and two RWD's for each DQ. This reduces the frequencies of the MDQ's and the RWD's to 1/8 and 1/2, respectively. A 1-V swing signaling on the RWD is used to reduce the burst current by 18 mA. The 1-V swing signaling is successfully converted to 2.1 V with self-timed first-in, first-out circuitry. The hardware data demonstrate 400-Mb/s/pin operation with a 16-mm TSOP-II package. Seamless burst operation at various frequencies has also been confirmed. These features result in a 1.6-Gb/s data rate for ×32 200-MHz DDR operation with a cell/chip area efficiency of 67.5%     

Turn-On and Turn-Off Characteristics of a 4.5-kV 3000-A Gate Turn-Off Thyristor

A 4.5-kV 3000-A gate turn-off (GTO) thyristor has been developed for use in high-power motor drive control equipment such as inverters and choppers. The high gate turn-off current of 3000 A is achieved by decreasing the variation of on-state voltages as well as turn-off times between segments which compose the GTO thyristor. This idea is supported by observation of infrared radiation during the turn-off process in the parallel operation of two segments with different on-state voltages or turn-off times. The parallel operation behavior is well simulated by a two-dimensional numerical simulation. Such design considerations and electrical characteristics of the newly developed high-power GTO thyristor are described. The device has a forward blocking capability of 4.5 kV, a maximum gate turn-off current of 3000 A, on-state voltage of 3.0 V at 3000 A, turn-on time of 10 ?s, and turn-off time of 25 ?s.