Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

Reliability of large periphery GaN-on-Si HFETs

GaN devices exhibit excellent potential for use in many RF applications. However, commercial acceptance of the technology has been hindered by the scarcity and non-statistical nature of reliability results. In this work we present a full device level reliability study of GaN-on-Si HFETs. Reliability results on this technology include three-temperature DC data that show an activation energy of 1.7 eV and an average failure time >10⁷ h at 150 °C. Additionally, long duration DC lifetest (30 000 device hours) and RF lifetest (4000 device hours) results demonstrate a repeatable low drift process. Environmental tests such as autoclave and ESD demonstrate the ruggedness of the material system and technology. Finally, initial failure analysis is discussed.     

Power transistors fabricated using isotopically purified silicon (/sup 28/Si)

It is well known that isotopic purification of group IV elements can lead to substantial increases in thermal conductivity due to reduced scattering of the phonons. The magnitude of the increase in thermal conductivity depends on the level of isotopic purification, the chemical purity, as well as the test temperature. For isotopically pure silicon (/sup 28/Si) thermal conductivity improvements as high as sixfold at 20 K and 10%-60% at room temperature have been reported. Device heating during operation results in degradation of performance and reliability (electromigration, gate oxide wearout, thermal runaway). In this letter, we discuss the thermal performance of packaged RF LDMOS power transistors fabricated using /sup 28/Si. A novel technique allows the cost effective deployment of this material in integrated circuit manufacturing. A clear reduction of about 5/spl deg/C-7/spl deg/C in transistor average temperature and a corresponding 5%-10% decrease in overall packaged device thermal resistance is consistently measured by infrared microscopy in devices fabricated using /sup 28/Si over natural silicon.     

On the mechanism for interface trap generation in MOS transistorsdue to channel hot carrier stressing

The classical concept and theory suggest that the degradation of MOS transistors is caused by interface trap generation resulting from “hot carrier injection.” We report three new experiments that use the deuterium isotope effect to probe the mechanism for interface trap generation in n-MOS transistors in the presence of hot hole and electron injection. These experiments show clearly that hot carrier injection into the gate oxide exhibits essentially no isotope effect, whereas channel hot electrons at the interface exhibit a large isotope effect. This leads to the conclusion that channel hot electrons, not carriers injected into the gate oxide, are primarily responsible for interface trap generation for standard hot carrier stressing     

Degradation of gain in bipolar transistors

In this paper hot carrier related aging of n-p-n bipolar transistors is investigated experimentally and theoretically in order to bring physical insight into the bipolar h_FE (common emitter current gain) degradation. Electrical stress experiments are performed on transistors with different base doping profiles at varying temperatures. Detailed process simulations are performed to determine the doping profiles of the base-emitter junction. Monte Carlo transport simulations are then performed at different temperatures and bias conditions to determine the electron and hole distribution functions in the base-emitter junction. AT&T's 0.8 μm BICMOS technology is used to fabricate the experimental bipolar structures. For this non-self aligned technology we attribute h_FE degradation to the presence of hot holes and secondary electrons which are generated by hot hole impact ionization. This feedback due to impact ionization has a dominant effect on the high energy tails of the distribution of both holes and electrons even when the overall current multiplication is low. Simple hot electron energy transport models do not contain the complexity to properly describe ionization feedback and carrier heating, and are therefore inadequate. An exponential dependence of the transistor lifetime on BV_EBO is deduced for constant voltage stress (V_stressEBO) conditions, confirming the importance of secondaries in the process of degradation     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

Improvement of hot carrier reliability with deuterium anneals formanufacturing multilevel metal/dielectric MOS systems

This paper discusses new experimental findings critical for process integration of deuterium post-metal anneals to improve channel hot carrier reliability in manufacturing multilevel metal CMOS integrated circuits. Detailed account of the deuterium process optimization experiments varying temperature, time, and ambient is given. Specifically, the first demonstration of the large hydrogen/deuterium isotope effect for multilevel metal/dielectric MOS systems is reported. Previous accounts of the isotope effect had been limited to CMOS structures with one-level of dielectric/metal and to about a 10 fold improvement in reliability. Deuterium, instead of hydrogen is introduced via an optimized post-metal anneal process to achieve a 50-100 fold improvement in transistor channel hot carrier lifetime. The benefits of the deuterium anneal are still observed even if the post-metal anneal is followed by the final SiN cap wafer passivation process. It is concluded that the deuterium post-metal anneal process is suitable for manufacturing high performance CMOS products and fully compatible with traditional integrated circuit processes     

n+-polysilicon gate PMOSFET's with indium dopedburied-channels

In this letter a n⁺-polysilicon gate PMOSFET with indium doped buried-channel is discussed, The gate length scaling of n ⁺-polysilicon gate buried-length PMOSFET's is limited by the channel punch-through effect. Designing shallow counter-doped layers (buried-channels) has been established as a means to reduce the undesirable short channel effects in these devices. Indium, an acceptor dopant in Si, has a low diffusion coefficient and implant statistics favorable for achieving shallow doping layers. Indium implants are explored (as an alternative to BF₂) to counter dope the n-tub for adjusting the threshold voltage. Devices are fabricated using AT&T's 0.5 μm CMOS technology but with t_ox=50 Å. Although no special effort has been made to optimize the n-tub or to take full advantage of the diffusion and implant characteristics of indium, excellent electrical results are obtained for devices with L_eff=0.25 μm. Improved V_th roll-off characteristics and reduced body effect (γ≈0.18 V^½ versus γ_B≈0.40 V^½) in indium implanted buried channels are demonstrated over BF₂ implanted buried channels for PMOSFET's with identical long channel threshold voltages. The effects of incomplete ionization (freeze-out) of the indium acceptor states on the electrical device characteristics are demonstrated by device simulations and measurements     

Silicon npn bipolar transistors with indium-implanted base regions

In this paper, silicon npn bipolar transistors with indium-implanted base regions are discussed. Polysilicon emitter bipolar transistors are fabricated using a standard 0.5-μm BIC-MOS process flow where the base BF₂ implant is replaced by an indium implant. In indium-implanted transistors, the integrated hole concentration (G_b) in the quasi-neutral base is reduced due to incomplete ionization of indium acceptor states. The novel utilization of this impurity freeze-out effect results in much increased collector currents and common-emitter transistor gains (h_fe) compared to boron-implanted transistors. Also, since indium acceptor states in depletion regions become fully ionized, the spreading of the reverse-biased collector-base junction depletion region into the transistor base (base-width modulation) is minimized. Hence, for indium base bipolar transistor an improved h_fe-V_A product is anticipated. Our first attempt at fabricating bipolar transistors with indium-implanted base regions resulted in devices with greatly increased collector current, impressive gains of h_fe≈1600, excellent collector current saturation characteristics, an Early Voltage of V_A≈10 V, h_fe-V_A product of 16000 (implying an extended device design space), base-emitter breakdown voltages of BV_EBO≈9.6 V, and a cut-off frequency of f_t=17.8 GHz     

Deuterium post-metal annealing of MOSFET's for improved hot carrierreliability

Low-temperature post-metallization anneals in hydrogen ambients are critical to CMOS fabrication technologies in reducing Si/SiO₂ interface trap charge densities by hydrogen passivation. In this letter we show that the hot carrier reliability (lifetime) of NMOS transistors can be increased by an order of magnitude when wafers are annealed in a deuterium ambient. This phenomenon can be understood as a kinetic isotope effect. The chemical reaction rates involving the heavier isotopes are reduced, and consequently, under hot electron stress, bonds to deuterium are more difficult to break than bonds to protium (H). However, the static chemical bonding (i.e., binding energies and excited states) is evidently the same for both hydrogen and deuterium. We measure identical transistor function after hydrogen and deuterium treatment before hot electron dynamics and resultant damage. Therefore, deuterium and hydrogen post-metal anneal processes are compatible with each other in semiconductor manufacturing. SIMS analysis proves that at typical anneal temperatures (400-450°C), deuterium diffuses rapidly through the interlevel oxides and accumulates at Si/SiO ₂ interfaces. Transistor speed versus reliability trade-off in CMOS device design is discussed in light of the findings of this study