A low-noise microwave oscillator employing a self-alignedAlGaAs/GaAs HBT

A study is made of the application of heterojunction bipolar transistors (HBTs) to low-noise microwave circuits. Design considerations and the low-noise performance of a Ku-band free-running oscillator using a self-aligned AlGaAs/GaAs HBT are described. The device has a novel structure in which, by utilizing SiO ₂ sidewalls, the base surface area, which is the main cause of low-frequency noise, is drastically reduced. For a collector current of 1 mA, the fabricated device has base current noise power densities of 4×10^-20, 6×10^-21, and 2.5×10^-21 A²/Hz at baseband frequencies of 1, 10, and 100 kHz, respectively. A prototype oscillator operating at 15.5 GHz has a measured output power of 6 dBm and SSB FM noise power densities of -34 dBc/Hz at 1 kHz, -65 dBc/Hz at 10 kHz, and -96 dBc/Hz at 100 kHz off-carrier, without using high-Q elements such as a dielectric resonator. The results of this study demonstrate the suitability of HBTs for low-phase-noise microwave and millimeter-wave oscillator applications     

A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wirelesscommunications networks

This paper concerns the design consideration, fabrication process, and performance results for an ultra-broadband, low-voltage, low-power, BiCMOS-based transceiver chip for cellular-satellite-LAN wireless communication networks. The transceiver chip incorporates an RF amplifier, a Gilbert down-mixer, and an IF amplifier in the receive path, and an IF amplifier, a Gilbert up-mixer, and an RF amplifier in the transmit path. For an RF frequency in the 1-10 GHz band and an IF frequency in the 100-1000 MHz band, the developed transceiver chip consumes less than 60 mW at 2 V, to yield a downconversion gain of 40 dB at 1 GHz and 10 dB at 10 GHz and an upconversion gain of 42 dB at 1 GHz and 11 dB at 10 GHz. To avoid possible start-up problems caused during “stand-by” to “enable” mode transition, a simple switching technique is employed for enabling either the receive or the transmit path, by changing the value of a reference voltage applied to both the down- and the up-mixers. While the developed transceiver chip exhibits the best performance for a dc supply voltage of 2 V, it shows a graceful degradation for a ±0.15 V voltage deviation. The transceiver's chip size is 1.04 mm×1.04 mm     

Novel process for emitter-base-collector self-aligned heterojunction bipolar transistor using a pattern-inversion method

A process for base-emitter-collector self-aligned HBTs using a pattern-inversion method is presented. A fabricated HBT has an emitter with a size of 1.5 × 10?m2 realised by employing a dry-etching method. Typical current gain for the fabricated HBT is 26.     

A flexible downlink scheduling scheme in cellular packet data systems

Fast downlink scheduling algorithms play a central role in determining the overall performance of high-speed cellular data systems, characterized by high throughput and fair resource allocation among multiple users. We propose a flexible channel-dependent downlink scheduling scheme, named the (weighted) alpha-rule, based on the system utility maximization that arises from the Internet economy of long-term bandwidth sharing among elastic-service users. We show that the utility as a function of per-user mean throughput naturally derives the alpha-rule scheme and a whole set of channel-dependent instantaneous scheduling schemes following different fairness criteria. We evaluate the alpha-rule in a multiuser CDMA high data rate (HDR) system with space-time block coding (STBC) or Bell Labs layered space-time (BLAST) multiple-input multiple-output (MIMO) channel. Our evaluation shows that it works efficiently by enabling flexible tradeoff between aggregate throughput, per-user throughput, and per-user resource allocation through a single control parameter. In other words the Alpha-rule effectively fills the performance gap between existing scheduling schemes, such as max-C/I and proportional fairness (PF), and provides an important control knob at the media-access-control (MAC) layer to balance between multiuser diversity gain and location-specific per-user performance.     

A K-band monolithic oscillator integrated with a buffer amplifierusing a device-circuit interaction design concept

We report on a high power, high efficiency, and small-size monolithic coplanar waveguide oscillator incorporating a single-stage buffer amplifier on the same chip. For the oscillator design, by changing RF current level through the device, the optimum load line was chosen in order to have an oscillation frequency insensitive to the effect of the subsequently connected amplifier, based on a device-circuit interaction concept. The amplifier, on the other hand, which was driven directly by the oscillator, was designed to achieve an overall high power and high efficiency operation. At 21 GHz, the output power of the developed chip recorded 17 dBm with an overall DC-RF efficiency of 22%. By changing the length of a source feedback line, the oscillation frequency was varied from 21 GHz to 26 GHz. For all cases, the output power remained higher than 16 dBm     

60-GHz monolithic down- and up-converters utilizing asource-injection concept

This paper deals with the design considerations, fabrication process, and performance of coplanar waveguide (CPW) heterojunction FET (HJFET) down- and up-converter monolithic microwave integrated circuits (MMIC's) for V-band wireless system applications. To realize a mixer featuring a simple structure with inherently isolated ports, and yet permitting independent port matching and low local oscillator (LO) power operation, a “source-injection” concept is utilized by treating the HJFET as a three-port device in which the LO signal is injected through the source terminal, the RF (or IF) signal through the gate terminal, and the IF (or RF) signal is extracted from the drain terminal. The down-converter chip incorporates an image-rejection filter and a source-injection mixer. The up-converter chip incorporates a source-injection mixer and an output RF filter. With an LO power and frequency of 7 dBm and 60.4 GHz, both converters can operate at any IF frequency within 0.5-2 GHz, with a corresponding conversion gain within -7 to -12 dB, primarily dominated by the related filter's insertion loss. Chip size is 3.3 mm×2 mm for the down-converter, and 3.5 mm×1.8 mm for the up-converter     

An interdigitated printed antenna for PC card applications

A quarter-wavelength diversity patch configuration for the 2.4-GHz ISM band PC card application is reported. The structure is based on partly interdigitation of two quarter wavelength separated patches through a set of fingers for achieving the required space diversity on single side printed substrate with an easy matching on 50 Ω, high cross-polarization and within a given maximum space of 30 mm×50 mm. Measured antenna patterns for the developed structure are the same as for a classical patch and the bandwidth for a VSWR less than two is 2% with a maximum gain of 1.5 dB. This antenna has been incorporated in a high-speed wireless LAN PC card system     

A sub-nanosecond resonant-type monolithic T/R switch formillimeter-wave systems applications

This paper is concerned with the design consideration, fabrication process, and performance of a V-band monolithic transmit/receive (T/R) switch for millimeter-wave wireless networks applications. The developed switch integrated circuit (IC) has a novel structure in which to pass a signal, it presents a parallel resonant circuit to the signal by forward biasing a pair of switching heterojunction FET's (HJFETs), but to block the signal, it presents a series resonant circuit to the signal by reverse biasing the switching HJFETs. With a control voltage of 0/3.2 V, the developed T/R switch exhibits a minimum insertion loss of 3.9 dB, a maximum isolation of 41 dB, and a high switching speed of 250 ps, over 57-61 GHz. The monolithic T/R switch chip size is 3.3 mm×1.7 mm     

LDPC-coded cooperative relay systems: performance analysis and code design

We treat the problem of designing low-density parity-check (LDPC) codes to approach the capacity of relay channels. We consider an efficient analysis framework that decouples the factor graph (FG) of a B-block transmission into successive partial FGs, each of which denotes a two-block transmission. We develop design methods to find the optimum code ensemble for the partial FG. In particular, we formulate the relay operations and the destination operations as equivalent virtual MISO and MIMO systems, and employ a binary symmetric channel (BSC) model for the relay node output. For AWGN channels, we further develop a Gaussian approximation for the detector output at the destination node. Jointly treating the relay and the destination, we analyze the performance of the LDPC-coded relay system using the extrinsic mutual information transfer(EXIT) chart technique. Furthermore, differential evolution is employed to search for the optimum code ensemble. Our results show that the optimized codes always outperform the regular LDPC codes with a significant gain; in the AWGN case, when Protocol-II is employed and the relay is close to the source, the optimized code performs within 0.1dB to the capacity bound.     

Differentiated TCP User Perception over Downlink Packet Data Cellular Systems

Current downlink scheduling algorithms in the (enhanced) third-generation (3G) cellular packet systems exploit instantaneous channel status of multiple users, but most of them are blind to traffic information. To improve TCP users' perception of quality-of-services (QoSs), characterized by response delay, goodput, and always-on connectivity, we propose a cross-layer hierarchical scheduler with traffic awareness and channel dependence to properly prioritize buffer and radio resource allocation among different TCP classes. The scheduler has two tiers: at the IP layer, an intrauser scheduler enhances a common practice, i.e., the DiffServ-based buffer management, by dequeuing same-user TCP packets according to per-class specified and measured responsiveness; at the MAC layer, an interuser scheduler transmits the dequeued packets by considering the opportunistic channel states, mean throughput, and class ID of all users. Both tiers consider the online measured throughput, a cross-layer metric, to achieve resource and performance fairness and TCP classification. Experiments show that, compared with (variations of) proportional fairness (PF) and other schemes, our scheduler can notably speed up time-critical interactive TCP services (HTTP and TELNET) or TCP slow-starts with minor cost to bulk file transfer (FTP) or long-lived flows. It offers scalable and low-cost TCP performance enhancement over the emerging cellular systems