A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance

Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell contains a matrix of lookup tables that either implement mathematics functions or a random-access memory. A hierarchical interconnection network supports data transfer within and between modules. We have created software tools that allow users to map algorithms onto the reconfigurable platform. This paper analyzes the implementation of several common benchmarks, ranging from floating-point arithmetic to a radix-4 fast Fourier transform. The results are compared to contemporary DSP hardware.     

Medium-Grain Cells for Reconfigurable DSP Hardware

Reconfigurable hardware contains an array of programmable cells and interconnection structures. Field-programmable gate arrays use fine-grain cells that implement simple logic functions. Some proposed reconfigurable architectures for digital signal processing (DSP) use coarse-grain cells that perform 16-b or 32-b operations. A third alternative is to use medium-grain cells with a word length of 4 or 8 b. This approach combines high flexibility with inherent support for binary arithmetic such as multiplication. This paper presents two medium-grain cells for reconfigurable DSP hardware. Both cells contain an array of small lookup tables, or ldquoelementsrdquo, that can assume two structures. In memory mode, the elements act as a random-access memory. In mathematics mode, the elements implement 4-b arithmetic operations. The first design uses a matrix of 4 times 4 elements and operates in bit-parallel fashion. The second design uses an array of five elements and computes arithmetic functions in bit-serial fashion. Layout simulations in 180-nm CMOS indicate that the parallel cell operates at 267 MHz, whereas the serial cell runs at 167 MHz. However, the parallel design requires over twice the area. The proposed medium-grain cells provide the performance and flexibility needed to implement DSP. To evaluate the designs, the paper estimates the execution time and resource utilization for common benchmarks such as the fast Fourier transform. The architecture model used in this analysis combines the cells with a pipelined hierarchical interconnection network. The end results show great promise compared to other devices, including field-programmable gate arrays.     

Imaging for dismantlement verification: Information management and analysis algorithms

The level of detail discernible in imaging techniques has generally excluded them from consideration as verification tools in inspection regimes. An image will almost certainly contain highly sensitive information, and storing a comparison image will almost certainly violate a cardinal principle of information barriers: that no sensitive information be stored in the system. To overcome this problem, some features of the image might be reduced to a few parameters suitable for definition as an attribute, which must be non-sensitive to be acceptable in an Information Barrier regime. However, this process must be performed with care. Features like the perimeter, area, and intensity of an object, for example, might reveal sensitive information. Any data-reduction technique must provide sufficient information to discriminate a real object from a spoofed or incorrect one, while avoiding disclosure (or storage) of any sensitive object qualities. Ultimately, algorithms are intended to provide only a yes/no response verifying the presence of features in the image. We discuss the utility of imaging for arms control applications and present three image-based verification algorithms in this context. The algorithms reduce full image information to non-sensitive feature information, in a process that is intended to enable verification while eliminating the possibility of image reconstruction. The underlying images can be highly detailed, since they are dynamically generated behind an information barrier. We consider the use of active (conventional) radiography alone and in tandem with passive (auto) radiography. We study these algorithms in terms of technical performance in image analysis and application to an information barrier scheme.     

An isotope identification injection study with GammaTracker

GammaTracker is a portable handheld radioisotope identifier using position sensitive CdZnTe detectors. High confidence isotope identification is possible on GammaTracker owing to the system’s relatively high energy resolution and count rate sensitivity. A study was undertaken to evaluate the isotope identification performance of a prototype unit. Background and source spectra for various nuclides were measured and then randomly sampled to simulate various integration times and source intensities. The resulting spectral data sets were then run through the isotope identification algorithm to determine the probability of detection and the false alarm rate for each nuclide. The process was repeated for various isotope identification input parameters until an optimized set was achieved. This paper presents results from the injection study.     

Real-Time Compton Imaging for the GammaTracker Handheld CdZnTe Detector

We are currently developing a handheld radioisotope identifier containing 18 position-sensitive CdZnTe crystals. In addition to isotope identification, the device performs basic Compton imaging to determine the location of suspected sources. This paper presents two computationally efficient algorithms for this purpose. The first algorithm traces individual Compton cones onto the unit sphere, whereas the second algorithm computes the intersection of two Compton cones and the unit sphere. Simulations demonstrate that the algorithms are suitable for determining the directionality, even with features such as uncertainty calculations omitted. The one-cone algorithm works more efficiently at high count rates, but the two-cone algorithm generates fewer image artifacts.     

A computational Fourier series solution of the BenDaniel-DukeHamiltonian for arbitrary shaped quantum wells

A new technique for solving the BenDaniel-Duke Hamiltonian using a Fourier series method is discussed. This method Fourier transforms the effective mass and potential profiles to calculate the eigenenergies and probability densities in transform space. Numerical solutions of the eigenenergies of a rectangular quantum well are compared to the finite difference, finite element, and transfer matrix methods. The eigenenergies of the envelope functions are computed and compared to the exact case made under a constant effective mass approximation for an asymmetric triangular and parabolic shaped quantum well. The necessity of using a variable effective mass in the BenDaniel-Duke Hamiltonian is shown by a comparison of the eigenenergies in the constant and variable effective mass cases. The Fourier series method is then used to analyze the effects of compositional gradients and electric fields on the eigenenergies and envelope functions for asymmetric coupled asymmetric triangular quantum wells