5-GHz 32-bit integer execution core in 130-nm dual-V/sub T/ CMOS

A 32-bit integer execution core containing a Han-Carlson arithmetic-logic unit (ALU), an 8-entry /spl times/ 2 ALU instruction scheduler loop and a 32-entry /spl times/ 32-bit register file is described. In a 130 nm six-metal, dual-V/sub T/ CMOS technology, the 2.3 mm/sup 2/ prototype contains 160 K transistors. Measurements demonstrate capability for 5-GHz single-cycle integer execution at 25/spl deg/C. The single-ended, leakage-tolerant dynamic scheme used in the ALU and scheduler enables up to 9-wide ORs with 23% critical path speed improvement and 40% active leakage power reduction when compared to a conventional Kogge-Stone implementation. On-chip body-bias circuits provide additional performance improvement or leakage tolerance. Stack node preconditioning improves ALU performance by 10%. At 5 GHz, ALU power is 95 mW at 0.95 V and the register file consumes 172 mW at 1.37 V. The ALU performance is scalable to 6.5 GHz at 1.1 V and to 10 GHz at 1.7 V, 25/spl deg/C.     

Integrated amorphous and polycrystalline silicon thin-filmtransistors in a single silicon layer

Using a masked hydrogen plasma treatment to spatially control the crystallization of amorphous silicon to polycrystalline silicon in desired areas, amorphous and polycrystalline silicon thin-film transistors (TFTs) with good performance have been integrated in a single film of silicon without laser processing. Both transistors are top gate and shared all process steps. The polycrystalline silicon transistors have an electron mobility in the linear regime of ~15 cm²/Vs, the amorphous silicon transistors have a linear mobility of ~0.7 cm²/Vs and both have an ON/OFF current ratios of >10⁵. Rehydrogenation of amorphous silicon after the 600°C crystallization anneal using another hydrogen plasma is the critical process step for the amorphous silicon transistor performance. The rehydrogenation power, time, and reactor history are the crucial details that are discussed in this paper     

Dough-Handling and Cookie-Making Properties of Wheat Flour–Watermelon Protein Isolate Blends

There is a growing interest in fortifying cereal-based products with proteins. In this study, protein isolates prepared from defatted seed meals of two watermelon cultivars, Mateera and Sugar baby, were blended with medium strength wheat flour at levels of 2.5% to 10%. Dough handling properties such as farinographic parameters, dough extensibility, pasting properties, textural and sensory properties of cookies revealed significant (p ≤ 0.05) changes in dough and cookies. Irrespective of watermelon cultivars, protein isolates at 5% and 10% levels, significantly (p ≤ 0.05) increased dough stability and mixing tolerance index while pasting properties decreased considerably with incorporation of 5% protein isolate in wheat flour. Similar changes were observed in textural, colour and sensory properties of cookies fortified with protein isolates. The protein content of cookies supplemented with protein isolates increased significantly (p ≤ 0.05) while a significant (p ≤ 0.05) decrease occurred in total carbohydrate content. Cookie fracture force (kg) significantly (p ≤ 0.05) increased above 5% fortification levels for both protein isolates. Cookie spread factor (W/T) increased with 2.5% to 7.5% fortification levels, but further increase in protein levels decreased spread factor. Sensory scores of cookies showed that protein isolates incorporation up to 7.5% were acceptable. This study revealed that watermelon protein isolates can be successfully incorporated in a range of cereal products to improve their protein quality and functionality.     

Thin-film transistors in polycrystalline silicon by blanket andlocal source/drain hydrogen plasma-seeded crystallization

Thin film n-channel transistors have been fabricated in polycrystalline silicon films crystallized using hydrogen plasma seeding, by using several processing techniques with 600 to 625°C or 1000°C as the maximum process temperature. The TFTs from hydrogen plasma-treated films with a maximum process temperature of 600°C, have a linear field-effect mobility of ~35 cm²/Vs and an ON/OFF current ratio of ~10⁶, and TFTs with a maximum process temperature of 1000°C, have a linear field-effect mobility of ~100 cm²/Vs and an ON/OFF current ratio of ~10⁷. A hydrogen plasma has also then been applied selectively a in the source and drain regions to seed large crystal grains in the channel. Transistors made with this method with maximum temperature of 600°C showed a nearly twofold improvement in mobility (72 versus 37 cm² /Vs) over the unseeded devices at short channel lengths. The dominant factor in determining the field-effect mobility in all cases was the grain size of the polycrystalline silicon, and not the gate oxide growth/deposition conditions. Significant increases in mobility are observed when the grain size is in order of the channel length. However the gate oxide plays an important role in determining the subthreshold slope and the leakage current