Accessing Egypt: making myths and producing web sites in cyber-Cairo

From an anthropological viewpoint, “accessibility” is not so much a technological and design project as it is a cultural construction, a cognitive schema through which graphic designers and technologists imagine audiences and create appropriate graphic designs that will be “accessible” to that audience. The ethnographer's task is the specification of key actors, institutions and discourses active in the making and remaking of accessibility in a given context. In this article, we examine how Egyptian Web producers at the turn of millennium (1999–2001) sought to design Web portals that would allow the “typical” Egyptian to easily access the World Wide Web. We argue, first, that Egyptian Web producers are deeply influenced by national and international discourses that frame IT as a national mission for socioeconomic development. Second, we found that in the absence of clear definitions of the Web audience, Web producers imagined a “typical” Egyptian that contradicted their own experiences of users of the Web. Finally, we found that Egyptian Web producers largely borrowed pre-existing models, using design elements to “inflect” their sites with an Egyptian motif. However, the conceptual models of access and related design strategies created by Egyptian Web producers were out of touch with Egyptian social realities, contributing to a collapse of most Web portal projects.     

Analogue motion estimation based upon a squaring circuit

Motion estimation (ME) is the most computationally demanding part of the digital video coding process. The use of analogue computational circuits in this application can offer reductions in size and power dissipation. However, analogue circuits are subject to variations which can reduce performance. In this paper the analogue non-idealities are considered, and results are presented for video conferencing applications. Furthermore, a compact MOS squaring circuit for use in analogue ME processors is proposed. The circuit makes use of the inherent square-law characteristic of the MOS transistor in saturation and features small area, low-power and low-voltage operation. Measurements from fabricated samples of the circuit were incorporated in system-level simulations. The results of the simulations confirmed the suitability of the circuit for the intended application.     

A low-power analog motion estimation processor for digital video coding

Analog circuit techniques can be beneficially applied to reduce the circuit complexity and power consumption of motion estimation processors for digital video encoding. However, analog circuits are sensitive to mismatch which affects motion estimation. This paper presents the design of an analog motion estimation processor which overcomes these limitations. A novel architecture is described featuring pixel reuse and input offset error cancellation. The proof-of-concept realization was fabricated in 0.8-/spl mu/m CMOS, and operates on 4/spl times/4 pixel blocks and a search area of 8/spl times/8 pixels. However, the architecture is scalable to larger block sizes and more advanced technologies. Measured results for various QCIF video sequences at 15-f/s showed excellent PSNR performance. The prototype dissipates 0.9 mW of power from a single 3-V power supply and occupies an area of 0.95 mm/sup 2/. Energy consumption is 1.51 nJ per motion vector.     

Motion estimation processor using mixed-signal approach

This paper describes the design, realization, and evaluation of a mixed-signal motion estimation processor using the full-search block-matching algorithm. The approach features digital I/O and a low-power, compact analog computational core. The proof-of-concept realization whose architecture incorporates pixel reuse, was fabricated in 0.8-/spl mu/m CMOS technology occupying 0.65 mm/sup 2/, and operates on 4 /spl times/ 4 pixel blocks and a search area of 8 /spl times/ 8 pixels. The processor achieves a low energy consumption per motion vector of 1.35 nJ and dissipates 0.8 mW from a 3-V power supply at QCIF 15 frames/s. The approach is intended for portable applications of digital video encoding.     

Low-voltage MOS linear transconductor/squarer and four-quadrant multiplier for analog VLSI

Analog computations such as four-quadrant multiplication, linear voltage-to-current conversion and sum-square or difference-square are fundamental for many analog signal processing systems. All these functions can be realized based on the principle of the linearized differential pair using floating-voltage sources. This paper describes an improved practical realization of this principle, which is particularly suited to analog VLSI computational systems. The proposed class-AB analog cells are very compact, exhibit low total harmonic distortion and low nonlinearity, have a wide bandwidth, and are compatible with low-power and low-voltage operation. A mathematical discussion on stability and harmonic distortion of the proposed realization is presented. Both simulated results and measurements from fabricated cell samples in a 0.8-/spl mu/m CMOS process are given. The described circuits operate from a single 2-V power supply.