Highly reliable testing of ULSI memories with on-chip voltage-downconverters

Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described. The first in an on-chip VDC tuning technique that adjusts internal V_CC to compensate for the monitored characteristics of the process parameters during repair analysis testing. The second is an operating-voltage margin test, performed at various internal V_CC levels during the water sort test (WT) and the final shipping test (FT)     

SOI-DRAM circuit technologies for low power high speed multigigascale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty     

A 34-ns 16-Mb DRAM with controllable voltage down-converter

A high-speed 16-Mb DRAM with high reliability is reported. A multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme were used to meet the requirements for high speed. A low-power hybrid internal power supply voltage converter with an accelerated life-test function is also proposed and was demonstrated. A novel substrate engineering technology, a retrograded well structure formed by a megaelectronvolt ion-implantation process, provides a simple process sequence and high reliability in terms of soft error and latch-up immunity.<>     

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with acharge-transfer presensing scheme

A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 V_cc bit-line precharge achieves a five times larger readout voltage and 40% improvement in sensing speed compared with conventional sensing schemes. Operation over a 1.2- to 3.3-V range is achieved. A nonreset row block control scheme (NRBC) for power-consumption improvement in data-retention mode is proposed which decreases the charge/discharge number of the row block control circuit. By combining CTPS and NRBC, the data-retention current is reduced by 75%     

A speed-enhanced DRAM array architecture with embedded ECC

An array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. Based on a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes practical array-embedded error checking and correcting (ECC) with little area penalty and no access overhead in the page mode. The array architecture is applied to a scaled-down 16-Mb DRAM and has achieved high performance     

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchicalsquare-shaped memory block and distributed bank architecture

This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 μm² cell and 581.8 mm² small die area are achieved using 0.15-μm CMOS technology. The ×61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described     

An experimental 256-Mb DRAM with boosted sense-ground scheme

In developing the 256-Mb DRAM, the data retention characteristics must inevitably be improved. In order for DRAM's to remain the semiconductor device with the largest production volume in the 256-Mb era, we must develop a cost effective device with a small chip size and a large process tolerance. In this paper, we propose the BSG (boosted sense-ground) scheme for data retention and FOGOS (folded global and open segment bit-line) structure for chip size reduction. We have fabricated an experimental 256-Mb DRAM with these technologies and obtained a chip size of 304 mm² and a performance of 34 ns access time     

400-MHz random column operating SDRAM techniques with self-skewcompensation

High-speed data transfer is a key factor in future main memory systems. DDR SDRAM (double-data-rate synchronous-DRAM) is one of the candidates for high-speed memory. In this paper we present three techniques to achieve a short access time and high data transfer rate for DDR-SDRAM's. First, a self-skew compensating technique enables 400-Mbit/s address and data detection. Second, a novel trihierarchical WL scheme realizes multibank operation without access or area penalties. Third, an interleaved array access path doubles the array operating frequency and it enables 400-MHz random column operation. A 16-bank 256-Mbit DDR SDRAM circuit has been designed, and the possibility of the realization of random column 200 MHz×32 DDR operation, namely, 1.6-Gbyte/s data rate operation, has been confirmed     

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register

A single 3.3-V 16-Mbit DRAM with a 135-mm/sup 2/ chip size has been fabricated using a 0.5- mu m twin-well process with double-metal wiring. The array architecture, based on the twisted-bit-line (TBL) array, includes suitable dummy and space word-line configurations which suppress the inter-bit-line noise and bring yield improvement. The multipurpose register (MPR) designed for the hierarchical data bus structure provides a line-mode test (LMT), copy write, and cache access capability. The LMT with on-chip test circuits using the MPR and a comparator creates a random test pattern and reduces the test time to 1/1000. A field shield isolation and a T-shaped stacked capacitor allow the layout of a 4.8- mu m/sup 2/ cell size with a storage capacitance of 35 fF. These techniques enable the 3.3-V 16-Mbit DRAM to achieve a 60-ns RAS access time and 300-mW power dissipation at 120-ns cycle time.<>     

Low voltage circuit design techniques for battery-operated and/orgiga-scale DRAMs

This paper describes a charge-transferred well (CTW) sensing method for high-speed array circuit operation and a level-controllable local power line (LCL) structure for high-speed/low-power operation of peripheral logic circuits, aimed at low voltage operating and/or giga-scale DRAMs. The CTW method achieves 19% faster sensing and the LCL structure realizes 42% faster peripheral logic operation than the conventional scheme, at 1.2 V in 15 Mb-level devices. The LCL structure realizes a subthreshold leakage current reduction of three or four orders of magnitude in sleep mode, compared with a conventional hierarchical power line structure. A negative-voltage word line technique that overcomes the refresh degradation resulting from reduced storage charge (Q_s) at low voltage operation for improved reliability is also discussed. An experimental 1.2 V 16 Mb DRAM with a RAS access time of 49 ns has been successfully developed using these technologies and a 0.4-μm CMOS process. The chip size is 7.9×16.7 mm² and cell size is 1.35×2.8 μm²