Monte Carlo Simulations of High-Performance Implant Free In0.3Ga 0.7As Nano-MOSFETs for Low-Power CMOS Applications

The potential performance of implant free heterostructure In_0.3Ga_0.7As channel MOSFETs with gate lengths of 30, 20, and 15 nm is investigated using state-of-the-art Monte Carlo (MC) device simulations. The simulations are carefully calibrated against the electron mobility and sheet density measured on fabricated III-V MOSFET structures with a high-kappa dielectric. The MC simulations show that the 30 nm gate length implant free MOSFET can deliver a drive current of 2174 muA/mum at 0.7 V supply voltage. The drive current increases to 2542 muA/mum in the 20 nm gate length device, saturating at 2535 muA/mum in the 15 nm gate length one. When quantum confinement corrections are included into MC simulations, they have a negligible effect on the drive current in the 30 and 20 nm gate length transistors but lower the 15 nm gate length device drive current at 0.7 V supply voltage by 10%. When compared to equivalent Si based MOSFETs, the implant free heterostructure MOSFETs can deliver a very high performance at low supply voltage, making them suitable for low-power high-performance CMOS applications     

Reduction of the self-forces in Monte Carlo simulations of semiconductor devices on unstructured meshes

When using an unstructured mesh for device geometry, the ensemble Monte Carlo simulations of semiconductor devices may be affected by unwanted self-forces resulting from the particle-mesh coupling. We report on the progress in minimisation of the self-forces on arbitrary meshes by showing that they can be greatly reduced on a finite element mesh with proper interpolation functions. The developed methodology is included into a self-consistent finite element 3D Monte Carlo device simulator. Minimising of the self-forces using the proper interpolation functions is tested by simulating the electron transport in a 10 nm gate length, 6.1 nm body thick, double gate metal-oxide-semiconductor field-effect transistor (MOSFET). We demonstrate the reduction in the self-force and illustrate the practical distinction by showing I-V characteristics for the device.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

3D Parallel Simulations of Fluctuation Effects in pHEMTs

The use of 3D simulations is essential in order to study the effects of fluctuations when devices are scaled to deep submicron dimensions. A 3D drift-diffusion device simulator has been developed to effectively simulate pseudomorphic high electron mobility transistors (pHEMTs) on a distributed memory multiprocessor computer. The drift-diffusion equations are discretized using a finite element method on an unstructured tetrahedral mesh. The obtained set of equations is solved in parallel on an arbitrary number of processors using the message-passing interface library. We have applied our simulator to a 120 nm pHEMT based on the Al_0.3Ga_0.7As/In_0.2Ga_0.8As interface and carried out a calibration to real experimental data.     

Effect of interface state trap density on the characteristics of n-type,enhancement-mode,implant-free In0.3Ga0.7As MOSFETs

The effect of interface state trap density, D_it, on the device characteristics of n-type, enhancement-mode, implant-free (IF) In_0.3Ga_0.7As MOSFETs [1], [2] has been investigated using a commercial drift-diffusion (DD) device simulation tool. Methodology has been developed to include arbitrary D_it distributions in the input simulation decks to more accurately fit the measured subthreshold characteristics of recently reported 1.0 μm gate length IF In_0.3Ga_0.7As MOSFETs [3]. The impact of interface states on a scaled 30 nm gate length IF MOSFET is also reported.     

Efficient three‐dimensional parallel simulations of PHEMTs

An efficient 3D semiconductor device simulator is presented for a memory distributed multiprocessor environment using the drift–diffusion (D–D) approach for carrier transport. The current continuity equation and the Poisson equation, required to be solved iteratively in the D–D approach, are discretized using a finite element method (FEM) on an unstructured tetrahedral mesh. Parallel algorithms are employed to speed up the solution. The simulator has been applied to study a pseudomorphic high electron mobility transistor (PHEMT). We have carried out a careful calibration against experimental I–V characteristics of the 120 nm PHEMT achieving an excellent agreement. A simplification of the device buffer, which effectively reduces the mesh size, is investigated in order to speed up the simulations. The 3D device FEM simulator has achieved almost a linear parallel scalability for up to eight processors. Copyright © 2005 John Wiley & Sons, Ltd.     

NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.     

Simulation Study of High Performance III-V MOSFETs for Digital Applications

We have studied the performance potential of an 80 nm physical gate length MOSFET with GaAs channel and high-k gate insulator using ensemble Monte Carlo simulations. The results show that a such device could deliver a 100–125% increase in the drive current compared to conventional MOSFETs with analogous channel lengths and device structure. This improvement is much higher than the 20–30% drive current increase in similar devices with strained Si channels on virtual SiGe substrates.     

Comments on “High Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm”

We have a number of issues with the above paper ldquoHigh Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Current Exceeding 1 A/mm,rdquo by Y. Xuan, Y. Q. Wu, and P. D. Ye, published IEEE Electron Device Letters in April 2008 which we wish to highlight.