Impact of Stone-Wales and lattice vacancy defects on the electro-thermal transport of the free standing structure of metallic ZGNR

We report the effect of topological as well as lattice vacancy defects on the electro-thermal transport properties of the metallic zigzag graphene nano ribbons at their ballistic limit. We employ the density function theory–Non equilibrium green’s function combination to calculate the transmission details. We then present an elaborated study considering the variation in the electrical current and the heat current transport with the change in temperature as well as the voltage gradient across the nano ribbons. The comparative analysis shows, that in the case of topological defects, such as the Stone-Wales defect, the electrical current transport is minimum. Besides, for the voltage gradient of 0.5 Volt and the temperature gradient of 300 K, the heat current transport reduces by \({\sim }62\,\%\) and \({\sim }50\,\%\) for the cases of Stones-Wales defect and lattice vacancy defect respectively, compared to that of the perfect one.     

Analysis of tunneling currents in multilayer black phosphorous and $$\hbox {MoS}_{2}$$ non-volatile flash memory cells

This paper presents a theoretical study of tunneling current density and the leakage current through multi-layer (stacked) trapping layer in the gate dielectric in MOS non-volatile memory devices. Two different 2D materials (\(\hbox {MoS}_{2}\) and black phosphorous) with a combination of high-k dielectric (\(\hbox {HfO}_{2}\)) have been used for the study with differently ordered stacks i.e., as trapping layer and substrate. The material properties of 2D materials like density of states, effective mass and band structure has been evaluated using density functional theory simulations. Using the Maxwell–Garnett effective medium theory we have calculated the effective barrier height, effective bandgap, effective dielectric constant and effective mass of the gate dielectric stacks. By applying WKB approximation in the multi-layer trapping layer we have studied the effect of the direct and Fowler–Nordheim tunneling currents. The leakage current in all the different stack combinations used has also been evaluated. The results obtained have shown to match the required dynamics of a memory device.     

Ab initio study of mono-layer 2-D insulators (X-(OH)2 and h-BN) and their use in MTJ memory device

The paper presents an ab initio study of the 2-D insulators and their effect on the performance of a magnetic tunnel junction memory (MTJ) device. MTJ devices has been considered as an alternate to the charge based data storage cells due to its spin-polarised operation and high scaling probability. The use of 2-D insulators like X-(OH)₂ (X: Ca and Mg) and h-BN (hexagonal-Boron Nitride) in such device would be interesting. The authors have calculated the band structures, density of states and effective mass of electrons and holes for the mono-layer of these three non-conventional 2-D insulators using the first principle calculations in density functional theory framework using Quantumwise ATK tool. The ab initio calculation yielded band gap (E_g) of 4.633, 4.685 and 4.249 eV for h-BN, Ca(OH)₂ and Mg(OH)₂, respectively. The effective mass of electrons was calculated as 0.621, 0.604 and 0.478 for single layer h-BN, Ca(OH)₂ and Mg(OH)₂, respectively. While for holes it is 0.834, 0.446 and 0.407, respectively for h-BN, Ca(OH)₂ and Mg(OH)₂. The MTJ device properties as tunneling-magneto resistance, differential TMR, parallel and anti-parallel resistance, differential resistance and spin transfer torque components (in-plane and out-of-plane) with these materials as composite dielectric has been reported in this paper using MTJ Lab tool. The performance of MTJ memory device with h-BN based composite dielectric is found better.

     

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.