Analysis and architecture design of variable block-size motion estimation for H.264/AVC

Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory.     

Reliability investigation of 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel

The authors have investigated the reliability performance of G-band (183 GHz) monolithic microwave integrated circuit (MMIC) amplifiers fabricated using 0.07-/spl mu/m T-gate InGaAs-InAlAs-InP HEMTs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel on 3-in wafers. Life test was performed at two temperatures (T/sub 1/ = 200 /spl deg/C and T/sub 2/ = 215 /spl deg/C), and the amplifiers were stressed at V/sub ds/ of 1 V and I/sub ds/ of 250 mA/mm in a N/sub 2/ ambient. The activation energy is as high as 1.7 eV, achieving a projected median-time-to-failure (MTTF) /spl ap/ 2 /spl times/ 10/sup 6/ h at a junction temperature of 125 /spl deg/C. MTTF was determined by 2-temperature constant current stress using /spl Delta/G/sub mp/ = -20% as the failure criteria. The difference of reliability performance between 0.07-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with pseudomorphic In/sub 0.75/Ga/sub 0.25/As channel and 0.1-/spl mu/m InGaAs-InAlAs-InP HEMT MMICs with In/sub 0.6/Ga/sub 0.4/As channel is also discussed. The achieved high-reliability result demonstrates a robust 0.07-/spl mu/m pseudomorphic InGaAs-InAlAs-InP HEMT MMICs production technology for G-band applications.     

Enterococcal bacteremia in a medical center

BACKGROUND: The enterococci have become important nosocomial pathogens. They can cause multiple site infections and enterococcal bacteremia becomes more frequently associated with a high mortality rate. Previous studies of enterococcal bacteremia showed a variety of results. To establish the significance and importance of enterococci as nosocomial pathogens in this hospital, to characterize their clinical pictures and to search for the risk factors for mortality, this retrospective study was performed. METHODS: There were 208 cases of enterococcal bacteremia which occurred from 1988 to 1992. Twenty-seven cases had no medical charts, dismissing possibility of evaluation. Finally, 181 cases of enterococcal bacteremia were analysed. RESULTS: One hundred and eighteen episodes were nosocomial infections. Polymicrobial bacteremia occurred in 68.5% of the patients and the most common co-isolate was Pseudomonas aeruginosa. Those patients (78.5%) with underlying diseases and malignancies were the most common underlying problems. The portal of entry could be found in 69.6 percent of patients, with the gastrointestinal tract the most common sources. Antimicrobial susceptibility testing showed high gentamicin resistance rate (89.5%), and ampicillin still had about 80 percent sensitivity rate. The group who received specific antibiotic therapy for enterococcus showed lower mortality (36.4% versus 47.6%). Only one case had infective endocarditis. Forty-nine patients suffered from septic shock, the cause of 30 deaths. Totally 75 patients died during hospitalization. Besides sepsis, another major cause of death was their underlying diseases itself. CONCLUSIONS: Enterococci have no doubt become important nosocomial pathogens and enterococcal bacteremia were associated with high mortality, especially in elderly patients with underlying diseases such as malignancy or diabetes. When clinically dealing with sepsis from the gastrointestinal or biliary tract, especially when previous cephalosporins therapy showed no response, the possibility of enterococcal bacteremia should always be considered.     

The Synthesis of Sulfated Titanium Oxide Nanotubes

TiO₂ nanotubes can be prepared in gram quantities by treating anatase TiO₂ powder with concentrated NaOH solution. These TiO₂ nanotubes acquired strong acidity after being impregnated with sulfuric acid solution and calcined at 300 °C. The anatase TiO₂ powder used to prepare the nanotube did not catalyze the esterification between cyclohexanol and acetic acid, while sulfated TiO₂ nanotubes were very reactive toward the esterification reaction.     

Minimum-energy multicast in mobile ad hoc networks using network coding

The minimum energy required to transmit one bit of information through a network characterizes the most economical way to communicate in a network. In this paper, we show that, under a layered model of wireless networks, the minimum energy-per-bit for multicasting in a mobile ad hoc network can be found by a linear program; the minimum energy-per-bit can be attained by performing network coding. Compared with conventional routing solutions, network coding not only allows a potentially lower energy-per-bit to be achieved, but also enables the optimal solution to be found in polynomial time, in sharp contrast with the NP-hardness of constructing the minimum-energy multicast tree as the optimal routing solution. We further show that the minimum energy multicast formulation is equivalent to a cost minimization with linear edge-based pricing, where the edge prices are the energy-per-bits of the corresponding physical broadcast links. This paper also investigates minimum energy multicasting with routing. Due to the linearity of the pricing scheme, the minimum energy-per-bit for routing is achievable by using a single distribution tree. A characterization of the admissible rate region for routing with a single tree is presented. The minimum energy-per-bit for multicasting with routing is found by an integer linear program. We show that the relaxation of this integer linear program, studied earlier in the Steiner tree literature, can now be interpreted as the optimization for minimum energy multicasting with network coding. In short, this paper presents a unifying study of minimum energy multicasting with network coding and routing.     

Optimum power-saving method for power MOSFET width of DC/DC converters

An optimum power metal-oxide-semiconductor field effect transistor (MOSFET) width technique is proposed for enhancing the efficiency characteristics of switching DC-DC converters. By implementing a one-cycle buck DC-DC converter, it is demonstrated that the dynamic power MOSFET width controlling technique has a much improved power reduction whether the load current is light or heavy. The maximum efficiency of the buck converter is ~92% with a 3% efficiency improvement for the heavy load condition. The efficiency is further improved by ~16% for the light load condition as a result of the power reduction from the large power MOSFET transistors. Also proposed is a new error-correction loop circuit to enable a better load regulation than that of previous designs. Compared with the adaptive gate driver voltage technique, the optimum power MOSFET width can achieve a significant improvement in power saving. It is also superior to the low-voltage-swing MOSFET gate drive technique for switching DC-DC converters     

Intravaginal Controlled Administration of Flurogestone Acetate: (III) Development of Rate-Control Vaginal Devices

A Rate-Control vaginal device was developed which overcomes the low bioavailability and unpredictable Q - t^1/2 type release and absorption rate profiles of flurogestone acetate delivered by the currently marketed Syncro-Mate pessary.

The in vitro release and vaginal absorption profiles from the Rate-Control vaginal device were run simultaneously, a linear Q - t relationship was obtained with a significant improvement in bioavailability. A mathematical model was developed to correlate the in vitro drug release and the vaginal absorption profiles of flurogestone acetate from the vaginal devices.

The design, development and the simultaneous release and absorption profiles of flurogestone acetate from this new vaginal device were outlined and discussed.     

Task Planning For A Mobile Robot In An Indoor Environment Using Object-oriented Domain Information

For a mobile robot to be practical, it needs to navigate in dynamically changing environments and manipulate objects in the environment with operating ease. The main challenges to satisfying these requirements in mobile robot research include the collection of robot environment information, storage and organization of this information, and fast task planning based on available information. Conventional approaches to these problems are far from satisfactory due to their requirement of high computation time. In this paper, we specifically address the problems of storage and organization of the environment information and fast task planning in the area of robotic research. We propose an special object-oriented data model (OODM) for information storage and management in order to solve the first problem. This model explicitly represents domain knowledge and abstracts a global perspective about the robot's dynamically changing environment. To solve the second problem, we introduce a fast task planning algorithm that fully uses domain knowledge related to robot applications and to the given environment. Our OODM based task planning method presents a general frame work and representation, into which domain specific information, domain decomposition methods and specific path planners can be tailored for different task planning problems. This method unifies and integrates the salient features from various areas such as database, artificial intelligence, and robot path planning, thus increasing the planning speed significantly     

A single-chip 12.7 Mchips/s digital IF BPSK direct sequencespread-spectrum transceiver in 1.2 μm CMOS

This paper describes a fully integrated digital-spread spectrum transceiver chip fabricated through MOSIS in 1.2 μm CMOS. It includes a baseband spread spectrum transmitter and a coherent intermediate frequency (IF) receiver consisting of a Costas loop, an acquisition loop for the pseudo-noise (PN) sequence, and a clock recovery loop with a 406.4 MHz onchip numerically controlled oscillator (NCO). The transceiver is capable of operating at a maximum IF sampling rate of 50.8 MS/s and a maximum chip rate of 12.7 R Mchips/s (Mcps) with selectable data rates of 100, 200, 400, and 800 kbps. At the maximum operating speed of 50.8 R MS/s, it dissipates 1.1 W. In an additive white Gaussian noise channel the IF receiver achieves a receiver output SNR within 1 dB of theory and can acquire code with a wide range of input SNR from -17 dB to over 30 dB. The transceiver chip has been interfaced to an RF up/down converter to demonstrate a wireless voice/data/video link operating in the 902-928 MHz band     

Dynamic programming implementation on array processor architectures

Dynamic Programming (DP) applies to many signal and image processing applications including boundary following, the Viterbi algorithm, dynamic time warping, etc. This paper presents an array processor implementation of generic dynamic programming. Our architecture is a SIMD array attached to a host computer. The processing element of the architecture is based on an ASIC design opting for maximum speed-up. By adopting a torus interconnection network, a dual buffer structure, and a multilevel pipeline, the performance of the DP chip is expected to reach the order of several GOPS. The paper discusses both the dedicated hardware design and the data flow control of the DP chip and the total array.This work was supported in part by the NATO, Scientific and Environmental Affairs Division, Collaborative Research Grant SA.5-2-05(CRG.960201)424/96/JARC-501.