A biomorphic digital image sensor

An arbitrated address-event imager has been designed and fabricated in a 0.6-/spl mu/m CMOS process. The imager is composed of 80 /spl times/ 60 pixels of 32 /spl times/ 30 /spl mu/m. The value of the light intensity collected by each photosensitive element is inversely proportional to the pixel's interspike time interval. The readout of each spike is initiated by the individual pixel; therefore, the available output bandwidth is allocated according to pixel output demand. This encoding of light intensities favors brighter pixels, equalizes the number of integrated photons across light intensity, and minimizes power consumption. Tests conducted on the imager showed a large output dynamic range of 180 dB (under bright local illumination) for an individual pixel. The array, on the other hand, produced a dynamic range of 120 dB (under uniform bright illumination and when no lower bound was placed on the update rate per pixel). The dynamic range is 48.9 dB value at 30-pixel updates/s. Power consumption is 3.4 mW in uniform indoor light and a mean event rate of 200 kHz, which updates each pixel 41.6 times per second. The imager is capable of updating each pixel 8.3K times per second (under bright local illumination).     

CMOS image sensors for sensor networks

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 μm CMOS process. The imagers embed an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low power operation. This characteristics allow the sensor to operate in different lighting conditions and for years on the sensor network node power budget. Eugenio Culurciello (S’97–M’99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from Johns Hopkins University, Baltimore, MD. In July 2004 he joined the department of Electrical Engineering at Yale University, where he is currently an assistant professor. He founded and instrumented the E-Lab laboratory in 2004. His research interest is in analog and mixed-mode integrated circuits for biomedical applications, sensors and networks, biological sensors, Silicon on Insulator design and bio-inspired systems. Andreas G. Andreou received his Ph.D. in electrical engineering and computer science in 1986 from Johns Hopkins University. Between 1986 and 1989 he held post-doctoral fellow and associate research scientist positions in the Electrical and Computer engineering department while also a member of the professional staff at the Johns Hopkins Applied Physics Laboratory. Andreou became an assistant professor of Electrical and Computer engineering in 1989, associate professor in 1993 and professor in 1996. He is also a professor of Computer Science and of the Whitaker Biomedical Engineering Institute and director of the Institute’s Fabrication and Lithography Facility in Clark Hall. He is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Between 2001 and 2003 he was the founding director of the ABET accredited undergraduate Computer Engineering program. In 1996 and 1997 he was a visiting professor of the computation and neural systems program at the California Institute of Technology. In 1989 and 1991 he was awarded the R.W. Hart Prize for his work on mixed analog/digital integrated circuits for space applications. He is the recipient of the 1995 and 1997 Myril B. Reed Best Paper Award and the 2000 IEEE Circuits and Systems Society, Darlington Best Paper Award. During the summer of 2001 he was a visiting professor in the department of systems engineering and machine intelligence at Tohoku University. In 2006, Prof. Andreou was elected as an IEEE Fellow and a distinguished lecturer of the IEEE EDS society. Andreou’s research interests include sensors, micropower electronics, heterogeneous microsystems, and information processing in biological systems. He is a co-editor of the IEEE Press book: Low-Voltage/Low-Power Integrated Circuits and Systems, 1998 (translated in Japanese) and the Kluwer Academic Publishers book: Adaptive Resonance Theory Microchips, 1998. He is an associate editor of IEEE Transactions on Circuits and Systems I.     

A Low-Power High-Speed Ultra-Wideband Pulse Radio Transmission System

We present a low-power high-speed ultra-wideband (UWB) transmitter with a wireless transmission test platform. The system is specifically designed for low-power high-speed wireless implantable biosensors. The integrated transmitter consists of a compact pulse generator and a modulator. The circuit is fabricated in the 0.5-mum silicon-on-sapphire process and occupies 420 mum times 420 mum silicon area. The transmitter is capable of generating pulses with 1-ns width and the pulse rate can be controlled between 90 MHz and 270 MHz. We built a demonstration/testing system for the transmitter. The transmitter achieves a 14-Mb/s data rate. With 50% duty cycle data, the power consumption of the chip is between 10 mW and 21 mW when the transmission distance is from 3.2 to 4 m. The core circuit size is 70 mum times 130 mum.     

Nano-Watt silicon-on-sapphire ADC using 2C-1C capacitor chain

An analogue-to-digital converter (ADC) in a 0.5 /spl mu/m silicon-on-sapphire CMOS technology is reported. This innovative ADC uses a 2C-1C capacitor chain and a switched capacitor comparator. The ADC is capable of sampling at 409 kS/s, consuming 900 nW at 1.1 V power supply and 1.35 /spl mu/W at 1.5 V. It uses an active area of 300/spl times/700 /spl mu/m/sup 2/ and 640/spl times/1070 /spl mu/m/sup 2/ with pads.     

Integrated patch-clamp biosensor for high-density screening of cell conductance

The first fully integrated implementation of a patch-clamp measurement system is presented. The system was implemented in a 0.5 mum silicon-on-sapphire process. The system can record cell membrane currents up to plusmn 20 nA, with an rms noise of 5 pA at 10 kHz bandwidth. The system can compensate for the capacitance and resistance of the pipette electrode, up to 20 pF and 4 MOmega, respectively. The die size is 1150 by 700 mum. The power consumption is 3.3 mW at 3.3 V.     

Arbitrated address-event representation digital image sensor

An 80×60 pixels arbitrated address-event imager has been designed and fabricated in a 0.6 μm CMOS process. The output bandwidth is allocated according to the pixel's demand. The imager has a large dynamic range: 200 dB (pixel) and 120 dB (array). The power consumption is 3.4 mW in uniform indoor light. The imager is capable of 8.3 K effective frames per second     

Efficient feedforward categorization of objects and human postures with address-event image sensors

This paper proposes an algorithm for feedforward categorization of objects and, in particular, human postures in real-time video sequences from address-event temporal-difference image sensors. The system employs an innovative combination of event based hardware and bio-inspired software architecture. An event-based temporal difference image sensor is used to provide input video sequences, while a software module extracts size and position invariant line features inspired by models of the primate visual cortex. The detected line features are organized into vectorial segments. After feature extraction, a modified line segment Hausdorff distance classifier combined with on-the-fly cluster-based size and position invariant categorization. The system can achieve about 90 percent average success rate in the categorization of human postures, while using only a small number of training samples. Compared to state-of-the-art bio-inspired categorization methods, the proposed algorithm requires less hardware resource, reduces the computation complexity by at least five times, and is an ideal candidate for hardware implementation with event-based circuits.     

A multichip neuromorphic system for spike-based visual information processing

We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 x 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.     

Monolithic digital galvanic isolation buffer fabricated in silicon on sapphire CMOS

A monolithic four-channel digital galvanic isolation buffer in the 0.5 /spl mu/m silicon on sapphire (SOS) CMOS technology is reported. Advantage is taken of the insulating properties of the sapphire substrate to integrate on the same die both the isolation structure and the interface electronics. Each isolation channel has been tested to operate at data rates over 100 Mbit/s. The system can tolerate ground bounces of 1 V//spl mu/s and is tested for 800 V isolation. The system includes an integrated isolation charge pump to power the input circuit and is hence capable of operating from a single 3.3 V power supply.