Express Virtual Channels with Capacitively Driven Global Links

Networks on chip must deliver high bandwidth at low latencies while keeping within a tight power envelope. Using express virtual channels for flow control improves energy-delay throughput by letting packets bypass intermediate routers, but EVCs have key limitations. Nochi (NoC with hybrid interconnect) overcomes these limitations by transporting data payloads and control information on separate planes, optimized for bandwidth and latency respectively.     

Thousand-Core Chips [Roundtable]

The 2007 Design Automation Conference (DAC) had a special session entitled "1000 Core Chips," which was organized by Radu Marculescu (Carnegie Mellon University) and Li-Shiuan Peh (Princeton University). This session examined some of the ramifications of multicore chip design from four perspectives: technology, architecture, programming, and design automation. In this roundtable, held immediately following the conference session, the presenters expounded on the future of multicore chips with respect to education, programming languages, operating systems, and design automation.     

A delay model for router microarchitectures

This article introduces a router delay model that takes into account the pipelined nature of contemporary routers and proposes pipelines matched to the specific flow control method employed. Given the type of flow control and router parameters, the model returns router latency in technology-independent units and the number of pipeline stages as a function of cycle time. We apply this model to derive realistic pipelines for wormhole and virtual-channel routers and compare their performance. Contrary to the conclusions of previous models, our results show that the latency of a virtual channel router doesn't increase as we scale the number of virtual channels up to 8 per physical channel. Our simulation results also show that a virtual-channel router gains throughput of up to 40 % over a wormhole router     

CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs

Contention in performance-critical shared resources affects performance and quality-of-service (QoS) significantly. While this issue has been studied recently in CMP architectures, the same problem exists in SoC architectures where the challenge is even more severe due to the contention of shared resources between programmable cores and fixed-function IP blocks. In the SoC environment, efficient resource sharing and a guarantee of a certain level of QoS are highly desirable. Researchers have proposed different techniques to support QoS, but most existing works focus on only one individual resource. Coordinated management of multiple QoS-aware shared resources remains an open problem. In this paper, we propose a class-of-service based QoS architecture (CoQoS), which can jointly manage three performance-critical resources (cache, NoC, and memory) in a NoC-based SoC platform. We evaluate the interaction between the QoS-aware allocation of shared resources in a trace-driven platform simulator consisting of detailed NoC and cache/memory models. Our simulations show that the class-of-service based approach provides a low-cost flexible solution for SoCs. We show that assigning the same class-of-service to multiple resources is not as effective as tuning the class-of-service of each resource while observing the joint interactions. This demonstrates the importance of overall QoS support and the coordination of QoS-aware shared resources.     

Toward Ideal On-Chip Communication Using Express Virtual Channels

Current on-chip networks use a packet-switched design with a complex router at every hop, which imposes significant communication energy, delay, and throughput overhead. we propose reducing energy and delay, and increasing throughput, using express virtual channels. packets traveling along these virtual express lanes, which connect distant nodes in the network, bypass intermediate routers, significantly reducing router overhead.     

A power model for routers: modeling Alpha 21364 and InfiniBand routers

As interconnection networks proliferate to many new applications, a low-latency high-throughput fabric no longer suffices. An architectural-level power model for interconnection network routers will let researchers and designers easily factor in power when exploring architectural tradeoffs.     

Guest Editors' Introduction: Tackling Key Problems in NoCs

This special issue highlights recent innovations in network on a chip (NoC) design. The four articles fall into two main thrusts: the first three focus on design methodology challenges in NoCs; the final article demonstrates a practical case study implementation of an NoC.     

Efficient phosphorescent white organic light-emitting devices incorporating blue iridium complex and multifunctional orange–red osmium complex

By using the unique properties of the efficient orange–red phosphorescent osmium complex in combination with an efficient blue phosphorescent Iridium complex, efficient white organic light-emitting devices with forward viewing efficiencies up to (17% photon/electron, 36 cd/A, 28 lm/W) and white organic light-emitting devices with color stability vs. brightness can be implemented. Results show that the osmium complex is a multi-functional material that not only has high emission efficiency, but also possesses the effective hole trapping capability, which is useful for balancing hole/electron transport and controlling the emission zones when doped at appropriate locations of the device.     

Guest Editors' Introduction: On-Chip Interconnects for Multicores

This special issue of IEEE Micro brings readers the latest advances in the field of on-chip interconnects for multicores. The guest editors specifically selected articles to focus on novel on-chip networks realized on actual silicon--partly to showcase a few silicon prototypes of on-chip networks being used in multicore processors and SoCs; partly to bring to attention the implementation issues facing architects and designers. Along with six articles that gather insights from the designers of actual on-chip interconnects for multicores, the special issue includes two articles that delve into the design infrastructure support for on-chip networks and an article that summarizes the grand research challenges for realizing next-generation on-chip networks and multicores.