Pattern Effect Removal Technique for Semiconductor-Optical-Amplifier-Based Wavelength Conversion

A technique to overcome pattern dependence in semiconductor-optical-amplifier-based wavelength converters is presented. The technique is based on a careful selection of red- and blue-shifted spectral components having complementary pattern effects in the output spectrum of a wavelength-converted signal. Significant signal quality improvements are reported at a bit rate of 40 Gb/s.     

Execution cache-based microarchitecture for power-efficient superscalar processors

This paper investigates a possible solution to the problem of power consumption in superscalar, out-of-order processors by proposing a new microarchitecture, specifically designed to reduce increasing power requirements of high-end processors. More precisely, we show that by modifying the well-established superscalar processor architecture, significant savings can be achieved in terms of power consumption. Our approach aims at limiting the growing amount of power used in a typical processor for dynamic optimizations (including out-of-order scheduling and register renaming). Our proposed approach achieves significant power savings by reusing as much as possible from the work done by the front-end of a typical superscalar, out-of-order pipeline, via the use of a special cache nested deeply into the processor structure. By reusing instructions that are already decoded, reordered, and have their registers already renamed, the front end of the pipeline can be turned off for large periods of time with significant savings in the overall power consumption. Experimental results show up to 35% (30% on average) savings in average energy per committed instruction, and 35% (20% on average) savings in energy-delay product, with about 9% average performance loss, over a large spectrum of SPEC95 and SPEC2000 benchmarks.     

Architectures for Silicon Nanoelectronics and Beyond

Although nanoelectronics won't replace CMOS for some time, research is needed now to develop the architectures, methods, and tools to maximally leverage nanoscale devices and terascale capacity. Addressing the complementary architectural and system issues involved requires greater collaboration at all levels. The effective use of nanotechnology calls for total system solutions     

"It's a small world after all": NoC performance optimization via long-range link insertion

Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.     

Challenges and Promising Results in NoC Prototyping Using FPGAs

Although a significant amount of theoretical work supports the potential of NoC architectures, such results need to be demonstrated by actual implementations before the NoC paradigm becomes a reality. Besides demonstrating the feasibility of the overall approach, prototyping enables accurate evaluation of power, performance, area, and various design trade-offs. This article presents four NoC prototypes, discusses the challenges associated with their design, and assesses the potential of the NoC approach.     

Microarchitecture-level power management

In this paper, we present a strategy for run-time profiling to optimize the configuration of a superscalar microprocessor dynamically so as to save power with minimum-performance penalty. The configuration of the processor is changed according to the parallelism and power profile of the running application. To identify the optimal configuration, additional hardware with minimal overhead is used to detect the parts of the running application which have good potential for energy savings. Experiments on some benchmark programs show good savings in total energy consumption; we have observed a mean decrease of 18% in average power, and 9% in total energy. Our proposed approach can be used for energy-aware computing in either portable applications or in desktop environments where power density is becoming a concern. This approach can also be incorporated in power-management strategies like advanced configuration and power interface (ACPI) as a replacement for classic thermal management schemes such as static-clock throttling. Our approach is shown to be better than static-throttling methods presently used in power management.     

Toward a multiple clock/voltage island design style for power-aware processors

Enabled by the continuous advancement in fabrication technology, present-day synchronous microprocessors include more than 100 million transistors and have clock speeds well in excess of the 1-GHz mark. Distributing a low-skew clock signal in this frequency range to all areas of a large chip is a task of growing complexity. As a solution to this problem, designers have recently suggested the use of frequency islands that are locally clocked and externally communicate with each other using mixed clock communication schemes. Such a design style fits nicely with the recently proposed concept of voltage islands that, in addition, can potentially enable fine-grain dynamic power management by simultaneous voltage and frequency scaling. This paper proposes a design exploration framework for application-adaptive multiple-clock processors which provides the means for analyzing and identifying the right interdomain communication scheme and the proper granularity for the choice of voltage/frequency islands in case of superscalar, out-of-order processors. In addition, the presented design exploration framework allows for comparative analysis of newly proposed or already published application-driven dynamic power management strategies. Such a design exploration framework and accompanying results can help designers and computer architects in choosing the right design strategy for achieving better power-performance tradeoffs in multiple-clock high-end processors.     

Synthesis and optical properties of water-soluble poly(vinylpyrrolidone) - modified fullerene C<Subscript>60</Subscript>

Summary  The effect of fullerene on the radical polymerization of N-vinylpyrrolidone with lauroyl peroxide in toluene was investigated kinetically. C₆₀ was found to act both as inhibitor and as retarder because the polymerization rate and the molecular weight of resulting poly(vinylpyrrolidone) is decreasing with the increase of the fullerene concentration (0-6.94 x 10^-4 mol l^-1). The water-soluble poly(vinylpyrrolidone)-modified fullerene C₆₀ compound was characterized by differential scanning calorimetric, Infrared and Raman spectroscopy, UV absorption and photoluminescence. Based on the results obtained by optical measurements, it is argued that by the covalent attachment of the polymeric radicals to fullerene cage the extended electronic conjugation system of the C₆₀ is broken leading to the appearance of a polyene structure.     

Electronic textiles: A platform for pervasive computing

The invention of the Jacquard weaving machine led to the concept of a stored "program" and "mechanized" binary information processing. This development served as the inspiration for C. Babbage's analytical engine-the precursor to the modern-day computer. Today, more than 200 years later, the link between textiles and computing is more realistic than ever. In this paper, we look at the synergistic relationship between textiles and computing and identify the need for their "integration" using tools provided by an emerging new field of research that combines the strengths and capabilities of electronics and textiles into one: electronic textiles, or e-textiles. E-textiles, also called smart fabrics, have not only "wearable" capabilities like any other garment, but also have local monitoring and computation, as well as wireless communication capabilities. Sensors and simple computational elements are embedded in e-textiles, as well as built into yarns, with the goal of gathering sensitive information, monitoring vital statistics, and sending them remotely (possibly over a wireless channel) for further processing. The paper provides an overview of existing efforts and associated challenges in this area, while describing possible venues and opportunities for future research.