Exact probabilistic testability measures for multi-output circuits

The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the X-gate, and applying to the resulting graph the analysis based on supergates.     

DYRE: a DYnamic REconfigurable solution to increase GPGPU’s reliability

The Journal of Supercomputing - General-purpose graphics processing units (GPGPUs) are extensively used in high-performance computing. However, it is well known that these devices’...     

Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs

The latest SRAM-based FPGA devices are making the development of low-cost, high-performance, re-configurable systems feasible, paving the way for innovative architectures suitable for mission- or safety-critical applications, such as those dominating the space or avionic fields. Unfortunately, SRAM-based FPGAs are extremely sensitive to Single Event Upsets (SEUs) induced by radiation. SEUs may alter the logic value stored in the memory elements the FPGAs embed. A large part of the FPGA memory elements is dedicated to the configuration memory, whose content dictates how the resources inside the FPGA have to be used to implement any given user circuit, SEUs affecting configuration memory cells can be extremely critics. Facing the effects of SEUs through radiation-hardened FPGAs is not cost-effective. Therefore, various fault-tolerant design techniques have been devised for developing dependable solutions, starting from Commercial-Off-The-Shelf (COTS) SRAM-based FPGAs. These techniques present advantages and disadvantages that must be evaluated carefully to exploit them successfully. In this paper we mainly adopted an empirical analysis approach. We evaluated the reliability of a multiplier, a digital FIR filter, and an 8051 microprocessor implemented in SRAM-based FPGA’s, by means of extensive fault-injection experiments, assessing the capability provided by different design techniques of tolerating SEUs within the FPGA configuration memory. Experimental results demonstrate that by combining architecture-level solutions (based on redundancy) with layout-level solutions (based on reliability-oriented place and route) designers may implement reliable re-configurable systems choosing the best solution that minimizes the penalty in terms of area and speed degradation.     

A System-layer Infrastructure for SoC Diagnosis

During IC manufacturing phase, discriminating between good and faulty chips is not enough. In fact, especially in the first phase of the production of a new device, a complete understanding of the possible failures is quickly required to ramp up production yield. For test engineers, dealing with the manufacturing test of Systems-on-chip (SoCs) means to tackle the extraction of diagnostic data from faulty chips. Another equally important aim of diagnosis, in a later step of a product lifecycle, is to find the real root cause of silicon misbehaviors for field returns. At the core test layer, the adoption of diagnosis-oriented Design-for-Testability structures is almost mandatory and many solutions have been worked out for several types of cores; diagnosis data retrieval often consists in the execution of a set of self-test procedures whose application order and/or customization may depend on the obtained results themselves. This paper details the characteristics of a system-layer test architecture able to manage efficiently SoC self-diagnostic procedures. This architecture is composed of a diagnosis-oriented Test Access Mechanism (TAM) and an Infrastructure-IP owning enough intelligence to automatically manage core diagnostic procedures. Both of them have been designed in compliance with the IEEE 1500 Standard for Embedded Core Test and exploit the characteristics of Self-Test structures inserted for the diagnosis of memory, processor and logic cores. This approach to SoC diagnosis minimizes ATE memory requirements for pattern storage and drastically speeds up the complete execution of diagnostic procedures. Experimental results highlight the convenience of the approach with respect to alternative ATE driven diagnosis procedures, while resorting to negligible area overhead.

New techniques for efficiently assessing reliability of SOCs

In this paper we propose an approach to speed-up Fault Injection campaigns for the evaluation of dependability properties of complex digital systems. The approach exploits FPGA devices for system emulation, and new techniques are described, allowing emulating the effects of faults and to observe faulty behavior. Thanks to its flexibility and efficiency, the approach is suitable to be applied to SOC devices. The paper points out the flexibility of the approach, able to inject different faults of different types in custom logic, memory blocks, and processor cores. The proposed approach combines the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that speed-up figures of up to 3 orders of magnitude with respect to state-of-the-art simulation-based techniques can be achieved.     

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art reliability estimation methods makes this exploration un-scalable with the design complexity. In this paper we introduce a low-cost reliability analysis methodology that helps taking this key decision with less computational effort and orders of magnitude faster. Based on this methodology we also propose a selective hardening technique using a hybrid fault tolerant architecture that allows meeting the soft-error rate constraints within a given design cost-budget and vice versa. Our experimental validation shows that the methodology offers huge gain (1200 ×) in terms of computational effort in comparison with fault injection-based reliability estimation method and produces results within acceptable error limits.     

Test Program Generation for Communication Peripherals in Processor-Based SoC Devices

Testing communication peripherals in an environment of systems on a chip is particularly challenging. The authors explore two test program generation approaches-one fully automated and one deterministically guided-and propose a novel combination of the two schemes that can be applied in a generic manner on a wide set of communication cores.     

Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test

A key issue in many safety-critical applications is the test of the ICs to be performed during the operational phase: regulations and standards often explicitly state the fault coverage figures to be achieved with respect to permanent faults. Functional test (i.e., a test exploiting only functional inputs and outputs, without resorting to any Design for Testability) is often the only viable solution, unless a strict cooperation exists between the system company and the device provider. However, purely functional test often shows several limitations due to the limited accessibility that it can gain on some input/output signals. This paper proposes a hybrid approach, in which a suitable hardware module is added outside a microcontroller to increase its functional testability during the operational phase. Experimental results gathered on several industrial cases-of-study are reported, showing the feasibility of the method.