Fast comparisons of circuit implementations

Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associated costs are not known prior to sizing. In this paper, we present two metrics for comparing different implementations-the minimum achievable delay and the cost of achieving a target delay-and show how these can be estimated without running a sizing tool. Using these fast and accurate performance estimators, a designer can determine the tradeoffs between multiple functionally identical implementations, and size only the selected implementation.     

Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing

As VLSI technologies scale down, interconnect performance is greatly affected by crosstalk noise due to the decreasing wire separation and increased wire aspect ratio, and crosstalk has become a major bottleneck for design closure. The effectiveness of traditional buffering and spacing techniques for noise reduction is constrained by the limited available resources on chip. In this paper, we present a method for incorporating crosstalk reduction criteria into global routing under a broad power supply network paradigm. This method utilizes power/ground wires as shields between signal wires to reduce capacitive coupling, while considering the constraints imposed by limited routing and buffering resources. An iterative procedure is employed to route signal wires, assign supply shields, and insert buffers so that both buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and buffer insertion are considered simultaneously via a dynamic programming-like approach. Our noise calculations are based on Devgan's metric, and our work demonstrates, for the first time, that this metric shows good fidelity on average. An effective noise margin inflation technique is also proposed to compensate for the pessimism of Devgan's metric. Experimental results on testcases with up to about 10000 nets point towards an asymptotic runtime that increases linearly with the number of nets. Our algorithm achieves noise reduction improvements of up to 53% and 28%, respectively, compared to methods considering only buffer insertion or only shield insertion after buffer planning.     

Building your yield of dreams [review of Design for Manufacturability and Yield for Nano-Scale CMOS by Charles Chiang and Jamil Kawa; 2007]

This is a review of Design for Manufacturability and Yield for Nano-Scale CMOS (by Charles Chiang and Jamil Kawa). DFM is a rapidly growing field that uses design techniques to improve manufacturing yield. However, the dilution in the interface between design and manufacturing implies that today, to build a circuit with enhanced yield, a designer must know more about manufacturing than ever before. The first step to embracing yield considerations is to learn about them, and this book portrays the landscape of this area in an excellent way. It describes methods for modeling variations, optimizing them, and learning to design around them when they occur. The overall structure of this book is well thought out and logical, and the reader who peruses it will be rewarded with an excellent view of the field.     

Placement and routing in 3D integrated circuits

Three-dimension technologies offer great promise in providing improvements in the overall circuit performance. Physical design plays a major role in the ability to exploit the flexibilities offered in the third dimension, and this article gives an overview of placement and routing methods for FPGA- and ASIC-style designs. We describe CAD techniques for placement and routing in 3D ICs, developed under our 3D analysis and design optimization framework. These approaches address a dichotomy of design styles, both FPGA and ASIC. The factors that are important in each style are different, so that a one-size-fits-all approach is impractical, and therefore, we present separate approaches for 3D physical design for each of these technologies. Hence, our FPGA placement method uses a two-step optimization process that minimizes inter-tier vias first, followed by further optimization within and across tiers. In contrast, the ASIC flow uses cost function weighting to discourage, but not minimize, inter-tier crossings.     

Surface-bound heparin fails to reduce thrombin formation during clinical cardiopulmonary bypass

The hypothesis that heparin-coated perfusion circuits reduce thrombin formation and activity; fibrinolysis; and platelet, complement, and neutrophil activation was tested in 20 consecutive, randomized adults who had cardiopulmonary bypass. Twenty identical perfusion systems were used; in 10, all blood-contacting surfaces were coated with partially degraded heparin (Carmeda process; Medtronic Cardiopulmonary, Anaheim, Calif.). All patients received a 300 U/kg dose of heparin. Activated clotting times were maintained longer than 400 seconds. Cardiopulmonary bypass lasted 36 to 244 minutes. Blood samples for platelet count, platelet response to adenosine diphosphate, plasma beta-thromboglobulin, inactivated complement 3b, neutrophil elastase, fibrinopeptide A, prothrombin fragment F1.2, thrombin-antithrombin complex, tissue plasminogen activator, plasminogen activator inhibitor-1, plasmin alpha 2-antiplasmin complex, and D-dimer were obtained at these times: after heparin was given, 5 and 30 minutes after cardiopulmonary bypass was started, within 5 minutes after bypass was stopped, and 15 minutes after protamine was given. After cardiopulmonary bypass, tubing segments were analyzed for surface-adsorbed anti-thrombin, fibrinogen, factor XII, and von Willebrand factor by radioimmunoassay. Heparin-coated circuits significantly (p < 0.001) reduced platelet adhesion and maintained platelet sensitivity to adenosine diphosphate (p = 0.015), but did not reduce release of beta-thromboglobulin. There were no significant differences between groups at any time for fibrinopeptide A, prothrombin fragment F1.2, or thrombin-antithrombin complex or in the markers for fibrinolysis: D-dimer, tissue plasminogen activator, plasminogen activator inhibitor-1, and alpha 2-antiplasmin complex. In both groups, concentrations of prothrombin fragment F1.2 and thrombin-antithrombin complex increased progressively and significantly during cardiopulmonary bypass and after protamine was given. Concentrations of D-dimer, alpha 2-antiplasmin complex, and plasminogen activator inhibitor-1 also increased significantly during bypass in both groups. Fibrinopeptide A levels did not increase during bypass but in both groups increased significantly after protamine was given. No significant differences were observed between groups for levels of inactivated complement 3b or neutrophil elastase. Radioimmunoassay showed a significant increase in surface-adsorbed antithrombin on coated circuits but no significant differences between groups for other proteins. We conclude that heparin-coated circuits used with standard doses of systemic heparin reduce platelet adhesion and improve platelet function but do not produce a meaningful anticoagulant effect during clinical cardiopulmonary bypass. The data do not support the practice of reducing systemic heparin doses during cardiac operations with heparin-coated extracorporeal perfusion circuitry.     

Body Bias Voltage Computations for Process and Temperature Compensation

With continued scaling into the sub-90-nm regime, the role of process, voltage, and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. These variations can cause the delay and the leakage of the chip to vary significantly from their expected values, thereby affecting the yield. Circuit designers have proposed the use of threshold voltage modulation techniques to pull back the chip to the nominal operational region. One such scheme, known as adaptive body bias (ABB), has become extremely effective in ensuring optimal performance or leakage savings. Our work provides a means to efficiently compute the body bias voltages required for ensuring high performance operation in gigascale systems. We provide a computer-aided design (CAD) perspective for determining the exact amount of bias voltages that can compensate both temperature and process variations. Mathematical models for delay and leakage based on minimal tester measurements are built, and a nonlinear optimization problem is formulated to ensure highest frequency operation under all conditions, and thereby minimize the overall circuit leakage. Three different algorithms are presented and their accuracies and runtimes are compared. The algorithms have been applied to a wide range of process and temperature corners, for a 65- and 45-nm technology node-based process. A suitable implementation mechanism has also been outlined.     

An EDA compendium

Reviewed in this issue The Electronic Design Automation Handbook, by Dirk Jansen (Kluwer Academic Publishers,2003, ISBN 1-402-07502-2, 244 pp., $148).     

Optimizing Decoupling Capacitors in 3D Circuits for Power Grid Integrity

This article studies one of the EDA problems for 3D IC design. The article presents a design automation solution for power grid optimization in 3D ICs. The authors propose a congestion-aware 3D power supply network optimization algorithm, which applies a sequence-of-linear-programs-based method to optimize the power grid design. We explore the trade-offs between MIM decaps and traditional CMOS decaps in chip design, and we propose a congestion-aware 3D power supply network optimization algorithm to optimize this trade-off. One of the novel features of our work is that it optimizes the power supply network using both conventional CMOS decaps and metal insulator-metal (MIM) decaps. However, because MIM decaps are built between layers of metal interconnects, they present routing blockages to nets that attempt to cross them, and therein lies the trade-off. The properties of MIM decaps make them attractive for both 2D and 3D chips, but we pay particular attention to the 3D decap problem in this article because, first, the power integrity problem is particularly critical in 3D, and requires novel approaches that leverage advances in materials, and second, the added complexity of handling routing blockages in a constrained environment makes the 3D problem especially challenging.