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DDS+PLL系统的频谱分析 总被引:4,自引:0,他引:4
简要介绍了 DDS+PLL频率合成的原理,分析了在 DDS没有相位截断误差时,DDS+PLL输出信号的杂散抑制度,并讨论了杂散抑制度与环路参数的关系。 相似文献
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高频数字锁相环的研究 总被引:5,自引:0,他引:5
论文阐述了100MHz数字锁相环的设计过程,用10MHz晶体振荡器对100MHz数字压控振荡器进行锁相,使100MHz输出信号指标得到很大改善。论文还分析了各单元电路,关键点时域波形测试,频谱测试。 相似文献
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This paper describes a brushless dc motor system without position or speed sensor. The brushless motor consists of a permanent magnet synchronous motor and a voltage-source inverter capable of controlling the amplitude and frequency of voltage. The rectangular-shaped stator current with a conducting interval of 120° (electrical) is controlled to be in phase with the trapezoidal back electromotive force. This results in producing maximum torque. Variable speed is achieved by adjusting the average motor voltage similarly to chopper control of dc motors. In this paper, two sensorless position detecting methods, i.e., an “indirect method” suited for the lower-speed range and a “direct method” suited for the higher-speed range are proposed. The combination of the two makes it possible to detect the rotor position over a wide-speed range. Furthermore, a speed-sen-sorless PLL control is proposed in applying the principle of the direct method. Experimental results obtained from a prototype brushless dc motor are shown to confirm the validity of the sensorless drive. The starting procedure of the motor also is discussed because it is impossible to detect the rotor position at a standstill. 相似文献
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芯片AD9854在跳频通信系统中的应用 总被引:7,自引:0,他引:7
介绍了AD公司新推出的AD9854芯片的主要特性,讨论了将其应用于跳频通信系统中的优势。 相似文献
8.
A 133-500 MHz,5.2 mW @500 MHz,0.021 mm2 all digital delay-locked loop(ADDLL)is presented.The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator(ROSC)to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed.The proposed ADDLL has better immunity to PVT(process,voltage,and temperature)than most conventional DLLs,which do not update the control word signals after the locking process,since the control signals for slave delay line are updated in every 256 reference cycles.Fabricated in 0.13 um CMOS process,the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps. 相似文献
9.
《Expert systems with applications》2014,41(2):622-634
This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm2 is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process. 相似文献
10.
《Computers & Electrical Engineering》2014,40(7):2113-2125
Due to increase in the number of Intellectual Property (IP) cores, clock generation in current day System-on-Chips (SoCs) is facing a crisis. The conventional method of using a dedicated Phase Locked Loop (PLL) to generate the clock for each IP core is becoming inefficient in terms of power and cost. We propose an algorithm based on Least Common Multiple (LCM) to minimize the number of PLLs required to generate the clocks for the IP cores in a SoC. This is done by finding an Optimum Operating Frequency (OOF) for each IP core within 10% below the maximum operating frequency of the core. The OOF is chosen such that the LCM of the OOF of all the IP cores is minimized. Simulated annealing is used to find the LCM. This LCM is the crucial high frequency from which maximum number of clocks can be derived by clock dividers. 相似文献