A review of the existing performance verification infrastructure for micro-CMMs

The performance verification of micro-CMMs is now of intense interest because of their capability to perform length measurements in three dimensions to high accuracy with low uncertainties. Currently, verification of micro-CMMs is completed in the spirit of existing specification standards, because strict adherence to these standards is often difficult. This review aims to present and discuss verification techniques available for micro-CMMs: specification standards, existing calibrated test lengths and traceability routes that can be associated with micro-CMMs. Three specification standards used in the testing of CMMs will be considered. In addition, a wide range of calibrated test lengths are reported, and any advantages and disadvantages associated with their use are discussed. It is concluded that micro-CMMs cannot yet be verified in accordance with existing specification standards. Suggestions are made for future standardisation work required to rectify these issues.     

使用FPGA与SDRAM实现液晶显示控制模块的浅析

针对液晶显示控制板上存储器(SRAM)存储量小和频率低的情况,提出了基于DDR sdram作为显示存储器的LCD显示控制器的设计。使用了灵活性与可靠性高的现场可编程门阵列(FPGA)来实现各模块的逻辑功能,分析了实现LCD显示屏控制模块的方案。     

Combined hardware–software multi-parallel prefiltering on the Convey HC-1 for fast homology detection

Protein databases used in research are huge and still grow at a fast pace. Many comparisons need to be done when searching similar (homologous) sequences for a given query sequence in these databases. Comparing a query sequence against all sequences of a huge database using the well-known Smith–Waterman algorithm is very time-consuming. Hidden Markov Models pose an opportunity for reducing the number of entries of a database and also enable to find distantly homologous sequences. Fewer entries are achieved by clustering similar sequences in a Hidden Markov Model. Such an approach is used by the bioinformatics tool HHblits. To further reduce the runtime, HHblits uses two-level prefiltering to reduce the number of time-consuming Viterbi comparisons. Still, prefiltering is very time-consuming. Highly parallel architectures and huge bandwidth are required for processing and transferring the massive amounts of data. In this article, we present an approach exploiting the reconfigurable, hybrid computer architecture Convey HC-1 for migrating the most time-consuming part. The Convey HC-1 with four FPGAs and high memory bandwidth of up to 76.8 GB/s serves as the platform of choice. Other bioinformatics applications have already been successfully supported by the HC-1. Limited by FPGA size only, we present a design that calculates four first-level prefiltering scores per FPGA concurrently, i.e. 16 calculations in total. This score calculation for the query profile against database sequences is done by a modified Smith–Waterman scheme that is internally parallelized 128 times in contrast to the original Streaming ‘Single Instruction Multiple Data (SIMD)’ Extensions (SSE)-supported implementation where only 16-fold parallelism can be exploited and where memory bandwidth poses the limiting factor. Preloading the query profile, we are able to transform the memory-bound implementation to a compute- and resource-bound FPGA design. We tightly integrated the FPGA-based coprocessor into the hybrid computing system by employing task-parallelism for the two-level prefiltering. Despite much lower clock rates, the FPGAs outperform SSE-based execution for the calculation of the prefiltering scores by a factor of 7.9.     

嵌入式实时操作系统内核混合代码的自动化验证框架

"如何构造高可信的软件系统"已成为学术界和工业界的研究热点.操作系统内核作为软件系统的基础组件，它的安全可靠是构造高可信软件系统的重要环节.为了确保操作系统内核的安全可靠，将形式化方法引入到操作系统内核验证中，提出了一个自动化验证操作系统内核的框架.该验证框架包括：（1）分别对C语言程序和混合语言程序（C语言和汇编语言）进行验证；（2）在混合语言程序验证中，为汇编程序建立抽象模型，并将C语言程序和抽象模型粘合形成基于C语言验证工具可接收的验证模型；（3）从规范中提取性质，基于该自动验证工具，对性质完成自动验证；（4）该框架不限于特定的硬件架构.成功地运用该验证框架对两种不同硬件平台的嵌入式实时操作系统内核μC/OS-II进行了验证.结果显示：利用该框架在对两个不同的硬件平台上内核验证时，框架的可重复利用率很高，高达到88%，虽然其抽象模型需要根据不同的硬件平台进行重构.在对基于这两种平台的操作系统内核验证中，分别发现了10~12处缺陷.其中，在ARM平台上两处与硬件相关的问题被发现.实验表明，该方法对不同硬件平台的同一个操作系统分析验证具有一定的通用性.     

Multi-resource scheduling for FPGA systems

In modern cloud data centers, reconfigurable devices (FPGAs) are used as an alternative to Graphics Processing Units to accelerate data-intensive computations (e.g., machine learning, image and signal processing). Currently, FPGAs are configured to execute fixed workloads, repeatedly over long periods of time. This conflicts with the needs, proper to cloud computing, to flexibly allocate different workloads and to offer the use of physical devices to multiple users. This raises the need for novel, efficient FPGA scheduling algorithms that can decide execution orders close to the optimum in a short time. In this context, we propose a novel scheduling heuristic where groups of tasks that execute together are interposed by hardware reconfigurations. Our contribution is based on gathering tasks around a high-latency task that hides the latency of tasks, within the same group, that run in parallel and have shorter latencies. We evaluated our solution on a benchmark of 37500 random workloads, synthesized from realistic designs (i.e., topology, resource occupancy). For this testbench, on average, our heuristic produces optimum makespan solutions in 47.4% of the cases. It produces acceptable solutions for moderately constrained systems (i.e., the deadline falls within 10% of the optimum makespan) in 90.1% of the cases.     

A scalable architecture for geometric correction of multi-projector display systems

Multi-projector displays allow the realization of large and immersive projection environments by allowing the tiling of projections from multiple projectors. Such tiled displays require real time geometrical warping of the content that is being projected from each projector. This geometrical warping is a computationally intensive operation and is typically applied using high-end graphics processing units (GPUs) that are able to process a defined number of projector channels. Furthermore, this limits the applicability of such multi-projector display systems only to the content that is being generated using desktop based systems. In this paper we propose a platform independent FPGA based scalable hardware architecture for geometric correction of projected content that allows addition of each projector channel at a fractional increase in logic area. The proposed scheme provides real time correction of HD quality video streams and thus enables the use of this technology for embedded and standalone devices.     

Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher

In this paper, low-cost and two-cycle hardware structures of the PRINCE lightweight block cipher are presented. In the first structure, we proposed an area-constrained structure, and in the second structure, a high-speed implementation of the PRINCE cipher is presented. The substitution box (S-box) and the inverse of S-box (S-box⁻¹) blocks are the most complex blocks in the PRINCE cipher. These blocks are designed by an efficient structure with low critical path delay. In the low-cost structure, the S-boxes and S-boxes⁻¹ are shared between the round computations and the intermediate step of PRINCE cipher. Therefore, the proposed architecture is implemented based on the lowest number of computation resources. The two-cycle implementation of PRINCE cipher is designed by a processing element (PE), which is a general and reconfigurable element. This structure has a regular form with the minimum number of the control signal. Implementation results of the proposed structures in 180-nm CMOS technology and Virtex-4 and Virtex-6 FPGA families are achieved. The proposed structures, based on the results, have better critical path delay and throughput compared with other's related works.     

低觉醒脑电识别与唤醒的可穿戴系统研究

为智能化地识别警戒作业人员出现的低觉醒、注意力下降的生理状态，本文介绍了一种基于FPGA和脑电信号处理的低觉醒状态检测与唤醒系统，系统通过传感器从大脑头皮采集脑电信号，转换为数字信号，经傅里叶变换获取了脑电信号的θ相对能量、α相对能量、重心频率、谱熵等4个特征量，由4个特征量表征低觉醒状态并运用支持向量机对低警戒状态进行识别，当识别出低觉醒状态时采用声音报警模块发出声音，唤醒警戒作业人员。设计系统能够较好地识别出低觉醒状态，识别率达90.8%，可为提高警戒作业工作绩效提供一种可穿戴的智能装备。     

一种新的解映射算法的推导和实现

本文在一种16QAM,64QAM,256QAM的解映射算法启发下,提出了新的适合32QAM和128QAM的解映射算法,并在此基础上,给出了适合DVB-C接收机的多QAM解映射结构.然后在FPGA中实现和仿真.最后通过比较说明,相对于传统的查找表解映射方法,提出的解映射算法可以明显减少资源使用率.