基于VHDL的CCD驱动时序设计

本文介绍了使用一种标准的硬件描述语言VHDL编写CCD驱动电路的新方法，给出了时序仿真波形，并验证了其可行性。     

0. 6 􀀁m CMOS 雷达天线专用控制芯片设计

雷达系统中天线控制电路完成上位机的初始化和扫描角度控制,要求具有高可靠性和低静态电流,用专用集成电路进行设计具有明显优势.采用Verilog HDL语言描述了系统的逻辑功能,超前进位结构的加/减法器提高了电路的工作速度.利用0.6 μm CMOS工艺完成了天线控制电路的物理实现,芯片面积为1.695 mm×1.631 mm.     

A Compositional Framework for Hardware/Software Co-Design

We describe a compositional framework, together with its supporting toolset, for hardware/software co-design. Our framework is an integration of a formal approach within a traditional design flow. The formal approach is based on Interval Temporal Logic and its executable subset, Tempura. Refinement is the key element in our framework because it will derivefrom a single formal specification of the system the software and hardware parts of the implementation, while preserving all properties of the system specification. During refinement simulation is used to choose the appropriate refinement rules, which are applied automatically in the HOL system. The framework is illustrated with two case studies. The work presented is part of a UK collaborative research project between the Software Technology Research Laboratory at the De Montfort University and the Oxford University Computing Laboratory.     

基于虚拟可重构平台的时序电路演化设计

目前,电路进化设计是演化硬件研究的主要方向之一。而时序电路由于存在反馈环不便于进行电路描述和软件仿真。文中对时序电路的演化设计方法进行了改进,提出了专门针对时序电路演化的虚拟可重构平台,建立起电路编码与HDL代码的映射关系。应用TEXTIO和MATLAB来辅助仿真测试过程,使测试向量数量巨大、难以处理的问题得到很好地解决。最后调用ModelSim完成了FSM的演化实验。实验结果验证了基于此平台演化时序电路的可行性和有效性。     

基于AMBA总线的IIC协议IP核设计与验证

介绍了一种基于AMBA总线verilogHDL实现的IIC主机模式的IP核设计。该模块能够在标准和快速模式下运行,能够灵活配置为十位地址寻址或七位地址寻址模式。详细说明了该IP核的架构,各部分设计及状态转换过程。最后该模块通过了系统验证,并在xilinxFPGA上转化为硬件电路实现了所有功能。     

数字可控正弦信号发生器的设计

该文采用DDS架构设计了可控正弦信号的产生方法。首先分析了数字可控正弦信号的基本原理;其次,采用Verilog HDL语言进行编程,在FPGA平台上进行了仿真及板级调试;最后,在示波器上得到了正确波形。该成果可用作一般信号处理过程的信号发生器,具有科学、准确、易实现,灵活及便携等优点。     

Mass spectrometric immunoassay and MRM as targeted MS-based quantitative approaches in biomarker development: Potential applications to cardiovascular disease and diabetes

Type 2 diabetes mellitus (T2DM) is an important risk factor for cardiovascular disease (CVD)—the leading cause of death in the United States. Yet not all subjects with T2DM are at equal risk for CVD complications; the challenge lies in identifying those at greatest risk. Therapies directed toward treating conventional risk factors have failed to significantly reduce this residual risk in T2DM patients. Thus newer targets and markers are needed for the development and testing of novel therapies. Herein we review two complementary MS-based approaches—mass spectrometric immunoassay (MSIA) and MS/MS as MRM—for the analysis of plasma proteins and PTMs of relevance to T2DM and CVD. Together, these complementary approaches allow for high-throughput monitoring of many PTMs and the absolute quantification of proteins near the low picomolar range. In this review article, we discuss the clinical relevance of the high density lipoprotein (HDL) proteome and Apolipoprotein A-I PTMs to T2DM and CVD as well as provide illustrative MSIA and MRM data on HDL proteins from T2DM patients to provide examples of how these MS approaches can be applied to gain new insight regarding cardiovascular risk factors. Also discussed are the reproducibility, interpretation, and limitations of each technique with an emphasis on their capacities to facilitate the translation of new biomarkers into clinical practice.     

基于FPGA的PCI总线目标接口IP核的设计

在芯片设计中采用IP(intellectual property)技术是IC设计发展到SOC时代的必然选择,建立IP库能为以后的设计节省大量的人力,提高设计效率.基于这样的思想,针对PCI接口使用的广泛性,讨论了基于FPGA的PCI总线目标接口IP核的设计技术.从PCI协议的介绍、总体设计思路、各功能模块设计、电路仿真等角度对IP核的设计方法进行了介绍,并着重介绍了状态机的设计.仿真的结果表明,该IP核在功能和时序上符合PCI技术规范,达到了预定的目标.     

基于FPGA的四相步进电动机控制器的设计

介绍了一种基于FPGA的四相步进电动机控制器的设计方案,给出了其控制原理、相关模块的设计及应用实例。该控制器采用全数字化控制,使用Verilog HDL语言编程,能够实现四相步进电动机的复位、脱机、转速和正反转控制。仿真及应用结果表明,该控制器控制灵活、调速范围大、精度高、运行稳定可靠。     

QoS保障机制中的FPGA堆排序实现

针对服务质量（QoS）的实现机制和严格动态优先级排序要求,在交换系统设计中引入一种易于FPGA实现的堆排序算法。采用模块化和状态机相结合的设计方法,给出模块的设计过程,利用XilinxISE8.2i＋ModerSim6.2软件对设计程序进行仿真,将程序下载到实验开发板上对系统进行验证,结果表明该设计的资源利用率高、运行速率快,适用于QoS机制的硬件实现。