Design and performance study of phase‐locked loop using fractional‐order loop filter

The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

单向实时数字视频传输中帧同步锁定技术研究

提出一种适用于单向实时数字视频传输系统的帧同步锁定方案。其方法在接收端采用本地参考时钟、状态机、锁相环，并结合CIMT编码方式实现系统自动维持帧同步锁定，而无需周期性加入帧同步码。对该帧同步锁定方案与周期性加入帧同步码强制锁定方案进行性能比较．并将其应用到单向实时数字视频光纤传输系统中。实验证明，系统自动实现帧同步锁定的方案是单向实时数字视频传输系统实现帧同步锁定的最佳方案。     

DDS+PLL系统的频谱分析

简要介绍了 ＤＤＳ＋ＰＬＬ频率合成的原理，分析了在 ＤＤＳ没有相位截断误差时，ＤＤＳ＋ＰＬＬ输出信号的杂散抑制度，并讨论了杂散抑制度与环路参数的关系。     

GM300电台的调试原理及方法

GM300电台是一种性能优良的电台，目前在我国的地震勘探领域广泛应用。与其它类型的电台相比，GM300电台的调试方法完全不同。掌握其调试原理及方法是对该类电台进行正确维护的基础。本文从分析GM300电台调试原理入手，总结了该电台的调试方法。     

高频数字锁相环的研究

论文阐述了１００ＭＨｚ数字锁相环的设计过程，用１０ＭＨｚ晶体振荡器对１００ＭＨｚ数字压控振荡器进行锁相，使１００ＭＨｚ输出信号指标得到很大改善。论文还分析了各单元电路，关键点时域波形测试，频谱测试。     

A sensorless brushless dc motor system

This paper describes a brushless dc motor system without position or speed sensor. The brushless motor consists of a permanent magnet synchronous motor and a voltage-source inverter capable of controlling the amplitude and frequency of voltage. The rectangular-shaped stator current with a conducting interval of 120° (electrical) is controlled to be in phase with the trapezoidal back electromotive force. This results in producing maximum torque. Variable speed is achieved by adjusting the average motor voltage similarly to chopper control of dc motors. In this paper, two sensorless position detecting methods, i.e., an “indirect method” suited for the lower-speed range and a “direct method” suited for the higher-speed range are proposed. The combination of the two makes it possible to detect the rotor position over a wide-speed range. Furthermore, a speed-sen-sorless PLL control is proposed in applying the principle of the direct method. Experimental results obtained from a prototype brushless dc motor are shown to confirm the validity of the sensorless drive. The starting procedure of the motor also is discussed because it is impossible to detect the rotor position at a standstill.     

数字频率合成技术在地球站中的应用

数字分频式微波频率合成器,具有结构简单,造价低,良好的低相嗓特性等优点,因而被通信卫星地球站所广泛采用。论述了数字分频式频率合成技术在工星通信地球站中的应用,提出了采用高度集成锁相环器件:PE3336设计一种低相噪特性的微波数字频率源的工程实例,并将之用于某通信卫星转发器地球站设备中。     

芯片AD9854在跳频通信系统中的应用

介绍了AD公司新推出的AD9854芯片的主要特性，讨论了将其应用于跳频通信系统中的优势。     

A low power and small area all digital delay-locked loop based on ring oscillator architecture

A 133-500 MHz,5.2 mW @500 MHz,0.021 mm2 all digital delay-locked loop(ADDLL)is presented.The power and area reduction of the proposed ADDLL are achieved by implementing a high frequency ring oscillator(ROSC)to count the reference clocks such that the one-clock cycle delay chain and the phase detector in a conventional Master block are no longer needed.The proposed ADDLL has better immunity to PVT(process,voltage,and temperature)than most conventional DLLs,which do not update the control word signals after the locking process,since the control signals for slave delay line are updated in every 256 reference cycles.Fabricated in 0.13 um CMOS process,the measured RMS jitter is 10.83 ps at 500 MHz while the RMS jitter of the input signal is 9.97 ps.     

A 5 GHz LC-VCO frequency synthesizer for unlicensed band of WiMAX

This paper presents a low power and low phase noise CMOS integer-N frequency synthesizer based on the charge-pump Phase Locked Loop (PLL) topology. The frequency synthesizer can be used for IEEE 802.16 unlicensed band of WiMAX (World Interoperability for Microwave Access). The operation frequency of the proposed design is ranged from 5.13 to 5.22 GHz. The proposed Voltage-Controlled Oscillator (VCO) achieves low power consumption and low phase noise. The high speed divider is implemented by an optimal extended true single phase clock (E-TSPC) prescaler. It can achieve higher operating frequency and lower power consumption. A new frequency divider is also proposed to eliminate the hardware overhead of the S counter in the conventional programmable divider. The proposed frequency synthesizer consists of a phase-frequency detector (PFD), a charge pump, a low-pass loop filter, a VCO, and a frequency divider. The simulated phase noise of the proposed VCO is −121.6 dBc/Hz at 1 MHz offset from the carrier frequency. The proposed frequency synthesizer consumes 13.1 mW. The chip with an area of 1.048 × 1.076 mm² is fabricated in a TSMC 0.18 μm CMOS 1P6M technology process.