2.3–21 GHz broadband and high linearity distributed low noise amplifier

This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S₂₁), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation and equalization of phase velocity techniques, to absorb their parasitic capacitances into the gate and drain transmission lines in order to achieve wide bandwidth and to enhance gain and linearity. The proposed broadband DA achieved an excellent gain in the flatness of 13.5 ± 0.2 dB, a low noise figure of 3.44 ± 1.12 dB, and a small group delay variation of ±19.721 ps over the range of 2.3–21 GHz. The input and output reflection coefficients S₁₁ and S₂₂ are less than −10 dB. The input compression point (P_1dB) and input third-order intercept point (IIP3) are −1.5 dBm and 11.5 dBm, respectively at 13 GHz. The dissipated power is 282 mW and the core layout size is 2.2 × 0.8 mm².     

使用FPGA与SDRAM实现液晶显示控制模块的浅析

针对液晶显示控制板上存储器(SRAM)存储量小和频率低的情况,提出了基于DDR sdram作为显示存储器的LCD显示控制器的设计。使用了灵活性与可靠性高的现场可编程门阵列(FPGA)来实现各模块的逻辑功能,分析了实现LCD显示屏控制模块的方案。     

Rethinking Enterprise Architecture for Sustainable Energy System Development

The development of a sustainable energy system throughout an enterprise is a complex task, which requires an agile holistic approach. Such an approach needs to include a variety of objectives including energy strategy formation and strategic decision-making, which are directly related to the analysis and management of the main areas of sustainable development:The economic, technological, environmental, and social. These multidimensional requirements of sustainability are often difficult to achieve within the enterprise, because these aspects are interrelated and influenced by various internal and external environment factors. This paper first reviews the main challenges for an energy system, and then demonstrates how a strategic agile enterprise architecture driven approach could effectively guide the sustainable energy system development. The study presented in this paper provides a holistic approach that contributes to the advancement and usage of literature dealing with issues of sustainable energy system development and agile enterprise architecture, which has not been discussed before to any great extent.     

Resistive switching characteristics of ZnO–graphene quantum dots and their use as an active component of an organic memory cell with one diode-one resistor architecture

We investigated the resistive switching characteristics of a polystyrene:ZnO–graphene quantum dots system and its potential application in a one diode-one resistor architecture of an organic memory cell. The log–log I–V plot and the temperature-variable I–V measurements revealed that the switching mechanism in a low-current state is closely related to thermally activated transport. The turn-on process was induced by a space-charge-limited current mechanism resulted from the ZnO–graphene quantum dots acting as charge trap sites, and charge transfer through filamentary path. The memory device with a diode presented a ∼10³ I_ON/I_OFF ratio, stable endurance cycles (10² cycles) and retention times (10⁴ s), and uniform cell-to-cell switching. The one diode-one resistor architecture can effectively reduce cross-talk issue and realize a cross bar array as large as ∼3 kbit in the readout margin estimation. Furthermore, a specific word was encoded using the standard ASCII character code.     

Combined hardware–software multi-parallel prefiltering on the Convey HC-1 for fast homology detection

Protein databases used in research are huge and still grow at a fast pace. Many comparisons need to be done when searching similar (homologous) sequences for a given query sequence in these databases. Comparing a query sequence against all sequences of a huge database using the well-known Smith–Waterman algorithm is very time-consuming. Hidden Markov Models pose an opportunity for reducing the number of entries of a database and also enable to find distantly homologous sequences. Fewer entries are achieved by clustering similar sequences in a Hidden Markov Model. Such an approach is used by the bioinformatics tool HHblits. To further reduce the runtime, HHblits uses two-level prefiltering to reduce the number of time-consuming Viterbi comparisons. Still, prefiltering is very time-consuming. Highly parallel architectures and huge bandwidth are required for processing and transferring the massive amounts of data. In this article, we present an approach exploiting the reconfigurable, hybrid computer architecture Convey HC-1 for migrating the most time-consuming part. The Convey HC-1 with four FPGAs and high memory bandwidth of up to 76.8 GB/s serves as the platform of choice. Other bioinformatics applications have already been successfully supported by the HC-1. Limited by FPGA size only, we present a design that calculates four first-level prefiltering scores per FPGA concurrently, i.e. 16 calculations in total. This score calculation for the query profile against database sequences is done by a modified Smith–Waterman scheme that is internally parallelized 128 times in contrast to the original Streaming ‘Single Instruction Multiple Data (SIMD)’ Extensions (SSE)-supported implementation where only 16-fold parallelism can be exploited and where memory bandwidth poses the limiting factor. Preloading the query profile, we are able to transform the memory-bound implementation to a compute- and resource-bound FPGA design. We tightly integrated the FPGA-based coprocessor into the hybrid computing system by employing task-parallelism for the two-level prefiltering. Despite much lower clock rates, the FPGAs outperform SSE-based execution for the calculation of the prefiltering scores by a factor of 7.9.     

Simplified anode architecture for PEMFC systems based on alternative fuel feeding: Experimental characterization and optimization for automotive applications

The need to reduce PEMFC systems cost as well as to increase their durability is crucial for their integration in various applications and especially for transport applications. A new simplified architecture of the anode circuit called Alternating Fuel Feeding (AFF) offers to reduce the development costs. Requiring a new stack concept, it combines the simplicity of Dead-End Anode (DEA) with the operation advantages of the hydrogen recirculation. The three architectures (DEA, recirculation and AFF) are compared in terms of performance on a 5-kW test bench in automotive conditions, through a sensitivity analysis. A gain of 17% on the system efficiency is observed when switching from DEA to AFF. Moreover, similar performances are obtained both for AFF and for recirculation after an accurate optimization of the AFF tuning parameters. Based on DoE data, a gain of 25% on the weight of the anodic line has been identified compared to pulsed ejector architecture and 43% with the classic recirculation architecture with blower only (Miraï).     

Multi-resource scheduling for FPGA systems

In modern cloud data centers, reconfigurable devices (FPGAs) are used as an alternative to Graphics Processing Units to accelerate data-intensive computations (e.g., machine learning, image and signal processing). Currently, FPGAs are configured to execute fixed workloads, repeatedly over long periods of time. This conflicts with the needs, proper to cloud computing, to flexibly allocate different workloads and to offer the use of physical devices to multiple users. This raises the need for novel, efficient FPGA scheduling algorithms that can decide execution orders close to the optimum in a short time. In this context, we propose a novel scheduling heuristic where groups of tasks that execute together are interposed by hardware reconfigurations. Our contribution is based on gathering tasks around a high-latency task that hides the latency of tasks, within the same group, that run in parallel and have shorter latencies. We evaluated our solution on a benchmark of 37500 random workloads, synthesized from realistic designs (i.e., topology, resource occupancy). For this testbench, on average, our heuristic produces optimum makespan solutions in 47.4% of the cases. It produces acceptable solutions for moderately constrained systems (i.e., the deadline falls within 10% of the optimum makespan) in 90.1% of the cases.     

A scalable architecture for geometric correction of multi-projector display systems

Multi-projector displays allow the realization of large and immersive projection environments by allowing the tiling of projections from multiple projectors. Such tiled displays require real time geometrical warping of the content that is being projected from each projector. This geometrical warping is a computationally intensive operation and is typically applied using high-end graphics processing units (GPUs) that are able to process a defined number of projector channels. Furthermore, this limits the applicability of such multi-projector display systems only to the content that is being generated using desktop based systems. In this paper we propose a platform independent FPGA based scalable hardware architecture for geometric correction of projected content that allows addition of each projector channel at a fractional increase in logic area. The proposed scheme provides real time correction of HD quality video streams and thus enables the use of this technology for embedded and standalone devices.