多处理器芯片体系结构研究

随着超大规模集成电路工艺和超级计算技术的发展，作者认为在单个芯片内集成多处理器系统将成为可能。本文详细讨论了多处理器芯片的分类和结构，着重阐述了同构型多处理器芯片的主要研究方向，并对同构型多处理器的可行性作出了分析。     

用Boltzmann网络解任务安排问题

本文提出了一种解任务安排问题的Ｂｏｌｔｚｍａｎｎ网络算法，已在Ｔｒａｎｓｐｕｔｅｒ多处理机系统上并行模拟实现，该算法具有优化程度高，运算速度快等特点．     

Fault tolerance in multiprocessor systems

Multiprocessor systems which afford a high degree of parallelism are used in a variety of applications. The extremely stringent reliability requirement has made the provision of fault-tolerance an important aspect in the design of such systems. This paper presents a review of the various approaches towards tolerating hardware faults in multiprocessor systems. It emphasizes the basic concepts of fault tolerant design and the various problems to be taken care of by the designer. An indepth survey of the various models, techniques and methods for fault diagnosis is given. Further, we consider the strategies for fault-tolerance in specialized multiprocessor architectures which have the ability of dynamic reconfiguration and are suited tovlsi implementation. An analysis of the state-of-the-art is given which points out the major aspects of fault-tolerance in such architectures.     

Unified reliability estimation and management of NoC based chip multiprocessors

We present a new architecture level unified reliability evaluation methodology for chip multiprocessors (CMPs). The proposed reliability estimation (REST) is based on a Monte Carlo algorithm. What distinguishes REST from the previous work is that both the computational and communication components are considered in a unified manner to compute the reliability of the CMP. We utilize REST tool to develop a new dynamic reliability management (DRM) scheme to address time-dependent dielectric breakdown and negative-bias temperature instability aging mechanisms in network-on-chip (NoC) based CMPs. Designed as a control loop, the proposed DRM scheme uses an effective neural network based reliability estimation module. The neural-network predictor is trained using the REST tool. We investigate how system’s lifetime changes when the NoC as the communication unit of the CMP is considered or not during the reliability evaluation process and find that differences can be as high as 60%. Full-system based simulations using a customized GEM5 simulator show that reliability can be improved by up to 52% using the proposed DRM scheme in a best-effort scenario with 2–9% performance penalty (using a user set target lifetime of 7 years) over the case when no DRM is employed.     

A new parallel lattice reduction algorithm for BKZ reduced bases

In order to implement the original BKZ algorithm in parallel,we describe it in terms of parallelism and give its parallel implementation scheme.Then we analyze the efficiency of algorithm’s parallel implementation and show that the speedup factor of BKZ algorithm in parallel is extremely low.Therefore we present a new parallel lattice reduction algorithm suitable for multiprocessor computer architecture.The new algorithm can obtain a BKZ reduced basis and the parallel speedup is effective.Also with the practical results,although the computational complexity increases compared with the original BKZ algorithm,we still indicate that the new algorithm performs well in parallel and the time cost in parallel is less.At the same time,we show that the length of the shortest vector is smaller.     

多选择软硬件划分问题的计算模型与动态规划算法

软硬件划分是软硬件协同设计的关键环节,划分的结果直接影响目标系统的设计质量。因此,对于一个给定的应用程序,为了使得目标系统快速执行且成本低廉,合理的划分策略十分重要。由于单个任务具有多种不同的硬件实现方式,与传统的单一硬件实现方式的软硬件划分问题相比,多选择的软硬件划分更能客观地反映现实应用。这导致问题的求解更具挑战性,它们已被证明是NP完全问题。基于多核处理器片上系统并针对任务图为二叉树的应用,建立了多选择软硬件划分问题的计算模型,并提出了解决该问题的动态规划算法。实验结果表明,当问题规模适中时,所提动态规划算法能够有效地获得精确解,并展示了算法的计算能力与硬件面积限制之间的关系。     

片上多核处理器容软错误执行模型

随着工艺的进步,微处理器将面临越来越严重的软错误威胁.文中提出了两种片上多核处理器容软错误执行模型:双核冗余执行模型DCR和三核冗余执行模型TCR.DCR在两个冗余的内核上以一定的时间间距运行两份相同的线程,store指令只有在进行了结果比较以后才能提交.每个内核增加了硬件实现的现场保存与恢复机制,以实现对软错误的恢复.文中选择的现场保存点有利于隐藏现场保存带来的时间开销,并且采用了特殊的机制保证恢复执行和原始执行过程中load数据的一致性.TCR执行模型通过在3个不同的内核上运行相同的线程实现对软错误的屏蔽.在检测到软错误以后,TCR可以进行动态重构,屏蔽被软错误破坏的内核.实验结果表明,与传统的软错误恢复执行模型CRTR相比,DCR和TCR对核间通信带宽的需求分别降低了57.5%和54.2%.在检测到软错误的情况下,DCR的恢复执行带来5.2%的性能开销,而TCR的重构带来的性能开销为1.3%.错误注入实验表明,DCR能够恢复99.69%的软错误,而TCR实现了对SEU(Single Event Upset)型故障的全面屏蔽.     

容错多处理机中一种高效的实时调度算法

针对基于主副版本容错的多处理机中独立的、抢占性的硬实时任务,提出了一种高效的调度算法——TPFTRM(task partition based fault tolerant rate-monotonic)算法.该算法将单机实时RM 算法扩展到容错多处理机上,并且调度过程中从不使用主动执行的任务副版本,而仅使用被动执行和主副重叠方式执行的任务副版本,从而最大限度地利用副版本重叠和分离技术提高了算法调度性能.此外,TPFTRM 根据任务负载不同将任务集合划分成两个不相交的子集进行分配;还根据处理机调度的任务版本不同,将处理机集合划分成3 个不相交的子集进行调度,从而使TPFTRM 调度算法便于理解、实现以及减少了调度所需要的运行时间.模拟实验对各种具有不同周期和任务负载的任务集合进行了调度测试.实验结果表明,TPFTRM与目前所知同类算法相比,在调度相同参数的任务集合时不仅明显减少了调度所需要的处理机数目,还减少了调度所需要的运行时间,从而证实了TPFTRM 算法的高效性.     

改进的基于目录的Cache一致性协议

介绍几种典型目录一致性协议并分析它们的优缺点。在综合全映射目录和有限目录优点的基础上,通过在存储器层上增加一个存储器高速缓存（Cache）层的方式,提出并讨论一种改进后的Cache一致性协议。该协议相对有限目录存储开销增加不多的情况下,提高了系统性能和可扩展性。     

基于Cortex嵌入式多处理器系统的图像中值滤波算法并行化的研究

嵌入式系统在图像处理、空间计算等领域越来越广泛,如何在功耗、成本和计算能力三个主要方面取得平衡,利用多核和多处理器系统以并行计算方式提高嵌入式系统计算能力是一种有效的解决方案.讨论了基于Cortex嵌入式多处理器系统的基本结构,并在该系统上进行图像中值滤波算法的并行化研究.实验结果分析表明,在该嵌入式多处理器平台上配合并行算法能够成倍提高图像中值滤波的运行性能.