一种简化逻辑电路设计的新器件EPLD

介绍了可以简化逻辑电路设计的可编程逻辑器件ＥＰＬＤ，详述了它的工作原理，开发工具，并且举例说明了应用ＥＰＬＤ设计电路的具体过程。     

静电放电人体模型测试标准EIA/JEDEC中的问题研究

通过具体的实例说明目前的静电放电（Electrostatic Discharge,ESD）人体模型测试标准EIA／JEDEC尚存在一些需要完善的问题。目前的标准EIA／JEDEC中缺少对起始测试电压的规定,导致有些测试直接从千伏（kV）量级的高压开始进行,造成一些设计不良的ESD防护器件在低压发生失效的状况可能被漏检的后果。本文研究对象为一个漏端带N阱镇流电阻（Nwell-ballast）的GGNMOS（Gate-Grounded NMOS）型ESD防护结构。用Zapmaster对它做人体模型（Human Body Model,HBM）测试,发现从1Kv起测时,能够通过8Kv的高压测试;而从50V起测时,却无法通过350V。TLP测试分析的结果显示此现象确实存在。本文详细剖析了该现象产生的机理,并采用OBIRCH失效分析技术对其进行了佐证。因该问题具有潜在的普遍性,因此提出了对目前业界广泛采用的EIA／JEDEC测试标准进行补充完善的建议。     

Investigation on thermal characteristics of heat sinks for power module using STM

The device that controls dynamic motions in a washing machine is called as MICOM. This device includes an IPM that controls the rotation of a tub. Also, the overheating of IPM gives cause for lowering the service life of an applied chip and is directly linked with its faults. A heat sink that is larger than the volume of the applied chip more than 50 times is installed to prevent such overheating. In the operation of the IPM, the temperature specification of the heat sink can be determined as 80°C under the air temperature of 25°C. However, the heat sink used at the present time cannot satisfy this condition, so it is necessary to redesign such a heat sink to satisfy this condition. This study proposes an STM that is able to precisely calculate the temperature applied to IPM in a system level prior to redesigning the heat sink. The STM can be considered as a model that complements a JEDEC analysis model. This model implements a parameter analysis to perform the optimization of a heat sink and verifies the priority of parameters to reduce material costs. Furthermore, it investigates a counterproposal that replaces the conventional cooling methods in which it seeks a counterproposal that performs heat dissipation in a device according to the SoC of chips and is able to suppress EMI. This paper was recommended for publication in revised form by Associate Editor Jae Dong Chung Chung-Hyo Jung acquired the doctoral degree in the Dept. of Science for Open and Enviromental Systems at Keio University in 2003. The specialty in the doctoral course was GSMAC-FEM and studied on MHD (magnetohydrodynamics). Dr. Jung joined Samsung Electronics Co., Ltd. as a CFD engineer in 2003. Also, he has worked at Samsung Advanced Institute of Technology and has charged in the thermal analysis of semi-conductors (system LSI). One of the Dr. Jung’s major concerning fields is the mechanical application of Lie-Groups.     

基于高性能数字芯片的多协议可编程接口设计

设计并制作了一种基于SMIC18混合信号工艺,可用于高性能数字芯片中的多协议、可编程输入接口电路.Cadence SPECTRE仿真及测试结果表明,电路可以在多种不同的JEDEC标准协议下工作并自由切换,并加入可控延迟,根据不同协议,电路可以编程选择不同的输入缓冲路径,在同一模块上集成10种JEDEC协议标准.电路同时可以在高至200 MHz的HSTL协议下工作,也可以满足LVTTL等协议的5 V耐压需求.     

Examination of board-level drop reliability of package-on-package stacking assemblies of different structural configurations

In this paper, we examine and compare numerically the board-level reliability of fan-in and fan-out package-on-package stacking assemblies subjected to a specific pulse-controlled drop test condition. The transient analysis follows the support excitation scheme and incorporates with an implicit time integration solver. Numerical results indicate that drop reliability of the package-on-package stacking assembly with a fan-out structural configuration is similar to that with a fan-in design.     

可编程逻辑器件GAL在设计数字式电子时钟中的应用

可编程逻辑器件GAL是80年代发展起来的新型器件，是一种由用户根据自己的需要来设计逻辑功能并对器件进行编程后实现的。数字式电子时钟是一个较为典型的数字逻辑电路。它采用可编程通用阵列逻辑GAL设计的数字式电子时钟可以满足使用者的一些特殊的要求，设计方式随意，输出方式灵活，如何以对时、分进行预置数控制；自行设置定时报警，单向或者逆向；倒计时；仿电台报时；置数或暂停功能。