在教学中推行微型化学实验势在必行

微型化学实验是当今化学教学中的重要变革之一。本文简单介绍了微型化学实验的特点和当前国内外发展的概况，倡议在我省的化学中尽快推行微型化学实验     

龙潭拱坝砼上坝运输方案选择

龙潭拱坝坝高９０ｍ，砼上坝运输是砼施工过程中的中间环节，控制进度的关键，必须因时因地制宜地选择适当的运输机械和运输方案，使砼运输能做到保质、保量、及时和经济，通过论证比较，结合本工程现实情况，砼上坝运输不采用缆机而采用门机方案．     

合体女裤提臀结构设计的探讨

首先用问卷调查的方式得到人们对合体裤提臀的要求,主要表现在臀突感、臀下以及臀后与人体的贴合度上;其后对6款样裤进行了拓版,得到影响提臀效果的结构设计参数.在此基础上用实验法得出结果:在合体裤制版参数常用取值范围内,总裆宽越小,后上裆倾斜角越大,前后裆宽比越小,裤子的提臀效果越好;通过美观性与舒适性的评价,得出兼顾两者的参数配置.     

Bit-level systolic arrays for modular multiplication

This paper presents bit-level cellular arrays implementing Blakley's algorithm for multiplication of twon-bit integers modulo anothern-bit integer. The semi-systolic version uses 3n(n+3) single-bit carry save adders and 2n copies of 3-bit carry look-ahead logic, and computes a pair of binary numbers (C, S) in 3n clock cycles such thatC+S[0, 2N). The carry look-ahead logic is used to estimate the sign of the partial product, which is needed during the reduction process. The final result in the correct range [0,N) can easily be obtained by computingC+S andC+S–N, and selecting the latter if it is positive; otherwise, the former is selected. We construct a localized process dependence graph of this algorithm, and introduce a systolic array containing 3nw simple adder cells. The latency of the systolic array is 6n+w–2, wherew=n/2. The systolic version does not require broadcast and can be used to efficiently compute several modular multiplications in a pipelined fashion, producing a result in every clock cycle.     

基于工作过程的“Flash动画”教学改革与实践

本文根据"Flash动画"课程的特点,结合学院的课程教学改革项目,从课程的教学理念、教学模式、教学体系和手段等方面着手,探讨了基于工作过程的教学改革与实践,以培养出符合新时代需要的创新人才。     

C-Testable modified-Booth multipliers

In this paper the testability of modified-Booth array multipliers for standard cells based design environments is examined for first time. In such cases the structure of the cells may be unknown, thus Cell Fault Model (CFM) is adopted. Two C-testable designs are proposed. A design for an N _x × N_y bits modified-Booth multiplier, which uses ripple carry addition at the last stage of the multiplication, is first proposed. The design requires the addition of only one extra primary input and 38 test vectors with respect to CFM. A second C-testable design is given using carry lookahead addition at the last stage which is the case of practical implementations of modified-Booth multipliers. Such a C-testable design using carry lookahead addition is for first time proposed in the open literature. This second design requires the addition of 4 extra primary inputs. One-level and two-levels carry lookahead adders, are considered. The C-testable design requires 61 test vectors for the former and 73 test vectors for the latter, respectively. The hardware and delay overheads imposed by both C-testable designs are very small and decrease when the size of the multiplier increases.     

基于组间进位预测的快速进位加法器

为加快密码系统中大数加法的运算速度,提出并实现一种基于组间进位预测的快速进位加法器。将参与加法运算的大数进行分 组,每个分组采用改进的超前进位技术以减少组内进位延时,组间通过进位预测完成不同进位状态下的加法运算,通过每个组产生的进位状态判断最终结果。性能分析表明,该进位加法器实现1 024位大数加法运算的速度较快。     

一种Ling选择进位加法器

设计一种Ling选择进位加法器,组间采用Ling进位代替传统的进位,利用内部连线与节点扇出平衡的并行前缀逻辑产生进位机制,并对通常的进位选择模块进行调整,以使其适合Ling进位。该加法器兼具了Ling加法器的快速性,又避免了逻辑产生的复杂性。实验结果表明,与超前进位加法器相比,该加法器的速度提高12％左右。     

PDCA循环与贯彻ISO9001:2000版标准

从贯彻ISO9001:2000版标准角度,阐述如何将PDCA循环理论应用于组织实现质量体系从ISO9000:1994标准到ISO9001:2000标准的转换。     

走向嵌入式因特网

简要介绍嵌入式系统,嵌入式因特网的概念,以及对嵌入式设备因特网接入的展望