A Fully Differential Interface Circuit of Closed-loop Accelerometer with Force Feedback Linearization

In this paper,a fifth-order fully differential interface circuit（ IC） is presented to improve the noise performance for micromechanical sigma-delta（ Σ-Δ） accelerometer. A lead compensator is adopted to ensure the stability of the closed-loop high-order system. A low noise capacitance detection circuit is described with a correlated-double-sampling（ CDS） technique to decrease 1 /f noise and offset of the operational amplifier. This paper also proposes a self-test technique for the interface circuit to test the harmonic distortion. An electrostatic force feedback linearization circuit is presented to reduce the harmonic distortion resulting in larger dynamic range（ DR）. The layout of the IC is implemented in a standard 0. 6 μm CMOS technology and operates at a sampling frequency of 250 kHz. The interface consumes 20 mW from a 5 V supply. The post-simulation results indicate that the noise floor of the digital accelerometer is about- 140 dBV /Hz1 /2at low frequency. The sensitivity is 2. 5 V /g and the nonlinearity is 0. 11%. The self-test function is achieved with 98. 2 dB thirdorder harmonic distortion detection based on the electrostatic force feedback linearization.     

一种新的连续时间Sigma-delta调制器系统设计方法

连续时间结构sigma-delta调制器中包括两种频域,是该结构设计的难点之一.本文在分析传统的连续时间调制器的设计流程后,提出一种新的设计方法.该方法增加了CT-DT变换,把连续时间环路滤波器转换到离散时间状态空间,利用离散时间调制器的成熟的设计平台进行设计,可以减少设计反复,加速设计收敛.利用该方法,本文设计了一个可用于手机电视的高速度、中高精度的连续时间sigma-delta调制器.     

Σ△微加速度计中基于脉宽调制的力反馈回路

针对微加速度计接口电路的sigma delta（ΣΔ）数字反馈系统,本文提出一种基于脉宽调制（PWM）的力反馈回路：利用模拟低通滤波器将PWM波解调成模拟输出信号,具有滤波和数模转换功能。首先建立了微加速度计ΣΔ闭环反馈系统的Simulink模型并进行了系统级仿真。之后采用Filter Solutions滤波器设计软件确定三阶低通巴特沃斯滤波器,并采用Pspice仿真软件进行电路级仿真。最后将制作的PCB版电路进行测试：PWM波通过力反馈回路能还原成高保真的模拟信号,输出信号和输入信号的频率相对误差小于0.36%,等效DAC分辨率为8位。试验表明,此方案结构简单、成本低,能以较低电路复杂度实现高精度的模拟信号输出。     

基于Σ-Δ调制技术的TWACS通信信号特征提取

针对双向工频自动通信系统(TwoWayAutomaticCommunicationSystem———TWACS)通信信号时域检测方法特征量少和抗干扰能力差,而时频分析方法数据处理复杂,装置成本高,提出了基于Σ-Δ增量调制技术提取TWACS通信信号的新方法.该方法在电网信号的调制区域将Σ-Δ调制器输出的1位数据流信息进行累加,将前后两抽样值的差值进行量化编码来代表连续信号所包含的信息,即采用增量调制的方式对相邻两个电网波形的位流和求差值来判断通信信号的有无,同时推导了有效的时域检测算法.对实际电网的测试表明,这种方案能够提取强干扰下电网中的调制信号,扩展了TWACS通信系统的应用范围.     

基于AD7708的卫星镍氢电池测试系统

介绍了基于∑-△的高性能模数转换器AD7708在航空电源测试中的应用，分析了∑-△型模数转换器的工作机理，重点讨论了AD7708所特有的斩波方式采样原理，在介绍系统整体架构的基础上，详细给出了系统采样部分硬件设计方法，提供了读取AD7708部分子程序的软件设计流程；而且结合实际电源的模拟试验要求，给出了对电池性能试验实现自动化测试的方法；最后，分析了系统电磁兼容性方面的设计要点，指出了一些特殊的抗干扰措施。系统测试精度达到0．5％。     

A high dynamic range analog-front-end IC for electrochemical amperometric and voltammetric sensors

A wide input range, compliant with electrochemical amperometric and voltammetric sensors analog-front-end (AFE) integrated circuit (IC) is proposed. The AFE employs current integrator (CI) and trans-impedance amplifier (TIA) to deal with the input current in the order of nA and μA separately, achieving the advantage of high dynamic range and high resolution. Input voltage is converted to current through a series of precise resistances, and detected by CI or TIA, which making the input voltage range is not limited by the power supply. An incremental sigma-delta ADC is employed to digitize the transferring signal, reducing the complexity and power dissipation. Compared to other alternatives, the AFE could handle current and voltage signals simultaneously, and input voltage range is not limited by power supply, showing high dynamic range and resolution. The AFE IC is fabricated in 0.18 μm 1P5M mixed-signal CMOS process, occupies an area of 3.2 mm×2 mm, the readout circuit has a dynamic range of 120 dB, consumes 4.2 mA.     

基于SIMULINK的开关型Σ-Δ调制器行为级建模

为精确反映多种非理想因素对开关型Σ-Δ调制器的影响,提高其在SIMULINK仿真器下的仿真精度,针对 SIMULINK的行为级建模提出一种新的积分器模型. 主要的改进之处包括：在运放模块中引入了有关直流增益非线性及信号建立过程非理想性的考虑,在开关模块中引入了电荷注入效应和导通阻抗的信号相关性影响,并将噪声模型作为独立模块引入系统. 应用该模型进行SIMULINK仿真,并与TSMC 0.35μm混合信号工艺下SPICE仿真结果进行比较验证.结果表明,所提出的模型成功地反映了上述因素对电路的重要影响,模型的应用提高了SIMULINK的仿真精度.     

Design of a high-order single-loop Σ△ ADC followed by a decimator in 0.18μm CMOS technology

This work presents an oversampled high-order single-loop single-bit sigma–delta analog-to-digital converter followed by a multi-stage decimation filter.Design details and measurement results for the whole chip are presented for a TSMC 0.18μm CMOS implementation to achieve virtually ideal 16-b performance over a baseband of 640 kHz.The modulator in this work is a fully differential circuit that operates from a single 1.8 V power supply. With an oversampling ratio of 64 and a clock rate of 81.92 MHz,the modulator achieves a 94 dB dynamic range. The decimator achieves a pass-band ripple of less than 0.01 dB,a stop-band attenuation of 80 dB and a transition band from 640 to 740 kHz.The whole chip consumes only 56 mW for a 1.28 MHz output rate and occupies a die area of 1×2 mm^2.     

80dB动态范围,用于低中频结构GSM接收机的∑△调制器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度∑△调制器.该调制器采用3阶单环单比特的结构,电路使用全差分开关电容结构实现,并在0.6μm 2P2M CMOS 工艺下流片验证.调制器使用全差分±1V参考电压,工作在26MHz采样频率,过采样率为64.测试结果表明,在200kHz信号带宽内,调制器达到80.6dB动态范围,峰值SNDR达到71.8dB,峰值SNR达到73.9dB.整个调制器电源电压为5V,静态功耗为15mW.     

Current Operational Amplifier (COA): CMOS Realization and Active Compensation

A methodology for analysis and synthesis of lowpass sigma-delta () converters is presented in this paper. This method permits the synthesis of modulators employing continuous-time filters from discrete-time topologies. The analysis method is based on the discretization of a continuous-time model and using a discrete simulator, which is more efficient than an analog simulator. In our analysis approach, the influence of the sample and hold block and non-idealities of the feedback DAC can be systematically modeled by discrete-time systems. Finally, a realistic design of a second-order modulator with a compensation of the non-ideal behavior of the DAC is given. Moreover, simulation results show a good agreement with the theoretical predictions.