Quantitative Evaluation of Register Pressure on Software Pipelined Loops

Software Pipelining is a loop scheduling technique that extracts loop parallelism by overlapping the execution of several consecutive iterations. One of the drawbacks of software pipelining is its high register requirements, which increase with the number of functional units and their degree of pipelining. This paper analyzes the register requirements of software pipelined loops. It also evaluates the effects on performance of the addition of spill code. Spill code is needed when the number of registers required by the software pipelined loop is larger than the number of registers of the target machine. This spill code increases memory traffic and can reduce performance. Finally, compilers can apply transformations in order to reduce the number of memory accesses and increase functional unit utilization. The paper also evaluates the negative effect on register requirements that some of these transformations might produce on loops.     

New structure of automatic torch and new approach for controlling drop transfer in rotating spray welding arc

Abstract

Using computer aided design/computer aided manufacturing technology, an automatic welding system is designed and manufactured for high current, high speed, and high deposition metal arc active gas (MAG) welding. The welding torch structure is evaluated and optimised via the finite element method and practical welding technology experiments. Finally, the process of high deposition MAG welding is investigated, and it is highlighted that on application of a longitudinal magnetic field to the high deposition MAG welding process, a steady metal transfer and drop deposition condition can be achieved, which is suited to the demands of high current, high speed welding technology.     

Capturing a Qualitative Model of Network Performance and Predicting Behavior

This paper describes a method for constructingbehavior models of communication networks. The methodutilizes archived quantitative performance data createdby a network management platform to create a Quantitative/Qualitative (Q²)Dynamic System representation. The Q²representation captures the predominant qualitative(symbolic) states of the network, qualitative inputevents and transitions among the states resulting from these events. Thissymbolic model allows the network manager to understandthe current system behavior, and predict future possiblebehaviors. We evaluated the method on two sets of archive data. The method shows promise foruse in network management, including network monitoring,fault detection, prognostication andavoidance.     

Parallel Programming and Performance Evaluation with the URSA Tool Family

This paper contributes to the solution of several open problems with parallel programming tools and their integration with performance evaluation environments. First, we propose interactive compilation scenarios instead of the usual black-box-oriented use of compiler tools. In such scenarios, information gathered by the compiler and the compiler's reasoning are presented to the user in meaningful ways and on-demand. Second, a tight integration of compilation and performance analysis tools is advocated. M any of the existing, advanced instruments for gathering performance results are being used in the presented environment and their results are combined in integrated views with compiler information and data from other tools. Initial instruments that assist users in data mining this information are presented and the need for much stronger facilities is explained. The URSA Family provides two tools addressing these issues. URSA MINOR supports a group of users at a specific site, such as a research or development project. URSA MAJOR complements this tool by making available the gathered results to the user community at large via the World-wide Web. This paper presents objectives, functionality, experience, and next development steps of the URSA tool family. Two case studies are presented that illustrate the use of the tools for developing and studying parallel applications and for evaluating parallelizing compilers.     

A New Digital Sense Multiple Access (DSMA) Protocol for High-Speed Wireless Networks

In this paper, we propose a new digital sensemultiple access with delayed transmission (DSMA/DT)protocol for reverse channel in high-speed wirelessnetworks. The new protocol is motivated by theobservation that the existing DSMA protocol does not yieldsatisfactory throughput for long round-trip propagationand processing delay, which occurs in outdoor high-speedenvironments or when the receiver hardware requires long signal processing time. The newDSMA/DT protocol is intended to reduce the performanceimpacts of the round-trip delay. Look-ahead busy/idleflag, seizure queueing, and reserved time slots are also devised for the new protocol. Whilerequiring at most two additional status bits on theforward channel and no additional hardware capability,these features further enhance the protocol performance and enable constant-bit-rate service withlittle added complexity in control. The channelthroughput of the DSMA/DT protocol and the optionalfeatures are analyzed. Closed-form expressions for thethroughput are obtained. For non-negligible round-tripdelay relative to packet transmission time, ournumerical results show that the new protocol improvesthe throughput by as much as 60% when compared to theexisting DSMA protocol. For superior performance andsimplicity, the DSMA/DT protocol will be appropriate foruse in high-speed wireless networks.