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The use of phase change materials (PCM) and their possible architectural integration is a path in the search for optimizing energy efficiency in construction. As part of this path, a pavement has been designed which, in combination with the PCM, serves as a passive thermal conditioning system (new patent n°. ES2333092 A1) [1]. The prototype has been tested experimentally and the results proved that it is a viable constructive solution improving the energy performance of sunny locals. 相似文献
3.
由于外墙瓷砖具有比涂料更好的耐污、耐久、耐水性。外墙瓷砖饰面深受人们的喜好。近年来随着建筑节能事业的进步,外墙外保温表面上粘贴瓷砖的工程也越来越多。但是在外墙外保温表面做瓷砖饰面是否可行,如何把握这项技术在建筑工程项目中的正确应用,是人们十分关注的技术关键问题,本文对此进行了多方面的计算,测试和分析,并从理论和实际施工两个方面做了进一步的说明。 相似文献
4.
根据风叶塑料件的尺寸结构特点,对风叶进行成型工艺分析,应用UG Mold Wizard模块完成了塑料件的分型设计及装配图设计。针对原有模具加工成型时出现的问题,重点对浇注系统、推出机构进行了结构改进,设计了环形浇口和瓦型推杆。为了提高工作零件加工制造的精度,型芯、型腔采用了镶拼组合式结构。生产实践证明,改进后的模具成型效果较好,推出机构灵活可靠,产品质量与合格率大大提升。 相似文献
5.
Seung-Joon Yoo Se-Il Lee Dong-Heui Kwak Kwang-Gil Kim Kyung-Jun Hwang Jae-Wook Lee Un-Yeon Hwang Hyung-Sang Park Jong-Ok Kim 《Korean Journal of Chemical Engineering》2008,25(5):1232-1238
Nanosized TiO2 sol synthesized by sol-gel method was successfully coated on the porous red clay tile (PRC tile) with micrometer sized pores.
PRC tile was first coated with a low-firing glaze (glaze-coated PRC tile) and then TiO2 sol was coated on the glaze layer. A low-fired glaze was prepared at various blending ratios with frit and feldspar, and
a blending ratio glazed at 700 °C was selected as an optimum condition. Then TiO2 sol synthesized from TTIP was dip-coated on the glazed layer (TiO2/glaze-coated PRC tile), and it was calcined again at 500 °C. Here, these optimum calcination temperatures were selected to
derive a strong bonding by a partial sintering between TiO2 sol particles and glaze layer. Photocatalytic activity on the TiO2/glaze-coated PRC tile was evaluated by the extent of photocatalytic degradation of methylene blue and acetaldehyde. Methylene
blue with the high concentration of 150 mg/l on the surface of TiO2/glaze-coated PRC tile was almost photodegraded within 5 hours under the condition of average UV intensity of 0.275 mW/cm2, while no photodegradation reaction of methylene blue occurred on the glaze-coated PRC tile without TiO2. Another photocatalytic activity was also evaluated by measuring the extent of photocatalytic degradation of gaseous acetaldehyde.
The photodegradation efficiency in TiO2/glaze-coated PRC tile showed about 77% photocatalytic degradation of acetaldehyde from 45,480 mg/l to 10,536 mg/l after the UV irradiation of 14 hours, but only about 16% in the case of the glaze-coated PRC tile. 相似文献
6.
陶瓷墙地砖坯体强度分析和强度影响因素及坯体压制特征探讨 总被引:3,自引:3,他引:0
根据力学理论综合分析了墙地砖坯体强度的形成机理及影响坯体强度的因素,如层裂、含湿度、致密度等.并对坯体强度与致密度;致密度与压制力及坯料之间的关系以及层裂对强度的影响进行了简要的分析.最后对满足坯体强度压制特征作了初步探讨. 相似文献
7.
Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates 下载免费PDF全文
Yongqiang Zhang Hongjun Lv Huakun Du Cheng Huang Shuai Liu Guangjun Xie 《International Journal of Circuit Theory and Applications》2016,44(7):1351-1366
Quantum‐dot cellular automata (QCA) is an emerging technology with the rapid development of low‐power high‐performance digital circuits. In order to reduce the wire crossings and the number of logic gates in QCA circuits, this paper proposes a full adder named Tile full adder based on a 3 × 3 grid module, a Tile bit‐serial adder based on the new full adder and a Diverse Clock Tile bit serial adder (DC Tile bit‐serial) adder based on the new full adder and a DC multiplier network. Based on previously mentioned circuit units an improved carry flow adder (CFA) named Tile CFA and two types of carry delay multiplier (CDM) named Tile CDM and DC Tile CDM (DC Tile CDM) with different sizes are presented. All of the proposed QCA circuits are designed and simulated with QCADesigner. Simulation results show that these circuit designs not only implement the logic functions correctly but also achieve a significant performance improvement. Copyright © 2015 John Wiley & Sons, Ltd. 相似文献
8.
Formalized study of self-assembly has led to the definition of the tile assembly model [Erik Winfree, Algorithmic self-assembly of DNA, Ph.D. Thesis, Caltech, Pasadena, CA, June 1998; Paul Rothemund, Erik Winfree, The program-size complexity of self-assembled squares, in: ACM Symposium on Theory of Computing, STOC02, Montreal, Quebec, Canada, 2001, pp. 459–468]. Research has identified two issues at the heart of self-assembling systems: the number of steps it takes for an assembly to complete, assuming maximum parallelism, and the minimal number of tiles necessary to assemble a shape. In this paper, I define the notion of a tile assembly system that computes a function, and tackle these issues for systems that compute the sum and product of two numbers. I demonstrate constructions of such systems with optimal Θ(1) distinct tile types and prove the assembly time is linear in the size of the input. 相似文献
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10.
At JET new plasma-facing components for the main chamber wall and the divertor are being designed and built to mimic the expected ITER plasma wall conditions in the deuterium-tritium operation phase. The main wall elements at JET will be made of beryllium and the divertor plasma-facing surface will be made of tungsten. Most of the divertor tiles will consist of tungsten-coated Carbon Fibre Composite (CFC) material. However one toroidal row in the outer divertor will be made of solid, inertially cooled tungsten. The geometry of these solid tungsten divertor components is optimized within the boundary conditions of the interfaces and the constraints given by the electrodynamical forces. Shadowing calculations as well as rough field line penetration analysis is used to define the geometry of the tungsten lamella stacks. These calculations are based on a set of magnetic equilibria reflecting the operation domain of current JET plasma scenarios. All edges in poloidal and toroidal direction are shadowed to exclude near perpendicular field line impact. In addition, the geometry of the divertor structure is being optimized so that the fraction of the plasma wetted surface is maximised. On the basis of the optimized divertor geometry, performance calculations are done with the help of ANSYS to assess the maximum power exhaust possible with this inertially cooled divertor row. 相似文献