Effects of apparent image velocity and complexity on the dynamic visual field using a high-speed train driving simulator

Train driving is a highly visual task. The visual capabilities of the train driver affects driving safety and driving performance. Understanding the effects of train speed and background image complexity on the visual behavior of the high-speed train driver is essential for optimizing performance and safety. This study investigated the role of the apparent image velocity and complexity on the dynamic visual field of drivers. Participants in a repeated-measures experiment drove a train at nine different speeds in a state-of-the-art high-speed train simulator. Eye movement analysis indicated that the effect of image velocity on the dynamic visual field of high-speed train driver was significant while image complexity had no effect on it. The fixation range was increasingly concentrated on the middle of the track as the speed increased, meanwhile there was a logarithmic decline in fixation range for areas surrounding the track. The extent of the visual search field decreased gradually, both vertically and horizontally, as the speed of train increased, and the rate of decrease was more rapid in the vertical direction. A model is proposed that predicts the extent of this tunnel vision phenomenon as a function of the train speed.Relevance to industryThis finding can be used as a basis for the design of high-speed railway system and as a foundation for improving the operational procedures of high-speed train driver for safety.     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Improving weld formability by a novel dual-rotation bobbin tool friction stir welding

A novel dual-rotation bobbin tool friction stir welding (DBT-FSW) was developed, in which the upper shoulder (US) and lower shoulder (LS) have different rotational speeds. This process was tried to weld 3.2 mm thick aluminum-lithium alloy sheets. The metallographic analysis and torque measurement were carried out to characterize the weld formability. Experimental results show that compared to conventional bobbin tool friction stir welding, the DBT-FSW has an excellent process stability, and can produce the defect-free joints in a wider range of welding parameters. These can be attributed to the significant improvement of material flow caused by the formation of a staggered layer structure and the unbalanced force between the US and LS during the DBT-FSW process.     

智能化中高压变频器实载试验平台的实现

中、高压变频器产量越来越多，但试验手段大多比较落后，一般采用带电机空转的方法。本文介绍了一个高压变频器试验平台，通过该平台可以对电压等级在3kV～10kV、功率在5000kW以下的变频器进行实载试验。     

超高压大容量铝电解电容器的研制

分析了大功率设备用超高压大容量铝电解电容器的特点,通过研制工作电解液、制订制作工艺及零部件设计方案,研制出的超高压大容量铝电解电容器具有损耗角正切小(tgδ为0.25)、承受纹波电流能力强(100 Hz,2.12～27.8 A)及寿命长的特点,耐久性达到85℃,5 000 h。     

MCF5282的I2C总线在uClinux操作系统下的驱动程序设计

介绍了Freescale公司嵌入式微处理器MCF5282的原理、特点,给出了该处理器在嵌入式操作系统uClinux下通过I2C硬件扩展数字输入的原理,以及I2C总线的驱动程序设计流程.     

Windows2000环境下实时控制系统的软件实现

文章介绍了在windows2000环境下通过编写WDM（Windows Driver Model）设备驱动程序实现实时数据采集和控制的一种方法。采用研华数据采集卡PCL818L产生中断信号．通过编写WDM驱动程序实现了在windows2000环境下转台的位置控制。并在实验中调试通过。实验结果表明：在采样频率为1KHz的情况下。控制系统很好实现了输出对输入的跟踪，证明了采用方法的正确性。该方法解决了windows2000环境下的实时性问题，为在windows环境下实时控制系统的实现提供了有益的尝试。     

Chemische Zusammensetzung und Mikrostruktur polymerabgeleiteter Gläser und Keramiken im System Si–C–O. Teil 2: Charakterisierung der Gefügeausbildung mittels hochauflösender Durchstrahlungselektronenmikroskopie und Feinbereichsbeugung

Chemical Composition and Microstructure of Polymer‐Derived Glasses and Ceramics in the Si–C–O System. Part 2: Characterization of microstructure formation by means of high‐resolution transmission electron microscopy and selected area diffraction Liquid or solid silicone resins represent the economically most interesting class of organic precursors for the pyrolytic production of glass and ceramics materials on silicon basis. As dense, dimensionally stable components can be cost‐effectively achieved by admixing reactive filler powders, chemical composition and microstructure development of the polymer‐derived residues must be exactly known during thermal decomposition. Thus, in the present work, glasses and ceramics produced by pyrolysis of the model precursor polymethylsiloxane at temperatures from 525 to 1550 °C are investigated. In part 1, by means of analytical electron microscopy, the bonding state of silicon was determined on a nanometre scale and the phase separation of the metastable Si–C–O matrix into SiO₂, C and SiC was proved. The in‐situ crystallization could be considerably accelerated by adding fine‐grained powder of inert fillers, such as Al₂O₃ or SiC, which permits effective process control. In part 2, the microstructure is characterized by high‐resolution transmission electron microscopy and selected area diffraction. Turbostratic carbon and cubic β‐SiC precipitate as crystallization products. Theses phases are embedded in an amorphous matrix. Inert fillers reduce the crystallization temperature by several hundred °C. In this case, the polymer‐derived Si–C–O material acts as a binding agent between the powder particles. Reaction layer formation does not occur. On the investigated pyrolysis conditions, no crystallization of SiO₂ was observed.