Design of Feedback Shift Register of Against Power Analysis Attack

Stream ciphers based on linear feedback shift register (LFSR) are suitable for constrained environments, such as satellite communications, radio frequency identification devices tag, sensor networks and Internet of Things, due to its simple hardware structures, high speed encryption and lower power consumption. LFSR, as a cryptographic primitive, has been used to generate a maximum period sequence. Because the switching of the status bits is regular, the power consumption of the LFSR is correlated in a linear way. As a result, the power consumption characteristics of stream cipher based on LFSR are vulnerable to leaking initialization vectors under the power attacks. In this paper, a new design of LFSR against power attacks is proposed. The power consumption characteristics of LFSR can be masked by using an additional LFSR and confused by adding a new filter Boolean function and a flip-flop. The design method has been implemented easily by circuits in this new design in comparison with the others.     

Optimal shift partitioning of pharmacies

The pharmacy service requires that some pharmacies are always available and shifts have to be organized: a shift corresponds to a subset of pharmacies that must be open 24 hours a day on a particular week. Under the requirement that each pharmacy belongs to exactly one shift and the assumption that users minimize the distance to the closest open pharmacy during each shift, we want to determine a partition of the pharmacies into a given number of shifts, such that the total distance covered by users is minimized. It may be also required that shift cardinalities are balanced. We discuss different versions and the related computational complexity, showing that the problem is NP-hard in general. A set packing formulation is presented and solved by branch-and-price, together with a fast solution technique based on a tabu search. They have been applied to real and random instances showing that (i) the set packing formulation is very tight and often exhibits no integrality gap; (ii) the branch-and-price solves problems of practical relevance to optimality in a reasonable amount of time (order of minutes); (iii) the tabu search finds optimal or near-optimal solutions in order of seconds.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

CRC计算方法的研究

本文丛面地介绍了ＣＲＣ的基本原理和计算方法，并给出了编程实例。     

基于移位原理的顺序控制器研究

本文根据PLC顺序控制程序的设计思路,阐述了用常用集成数码移位寄存器、电力电子开关电路和少量外围电子元件构成移位控制器的原理,根据此设计思路制作的移位控制器经过在实验室环境下运行,证明了设计方案的可行性。     

移动IP的关键技术

本详细描述了移动IP的工作过程，并介绍了移动IP的隧道技术和IPSec，最后对移动IP技术中存在几个热点问题进行了讨论。     

扫描式X光机及DDS在其运动控制中的应用

扫描式X光机是一种高精度，高性能的新型医疗设备，其显著优点在于大大降低了患者所受X光辐射剂量，可直接得到患者清晰的X光数字图像，缩短出片时间，X光片资料存储方便，便于实现远程诊断，该设备对运动控制部分的匀速性，平稳性和多次扫描的位置重复性的要求均很高。本文主要针对其运动控制部分的结构特点，分析了影响运动性能的主要原因，并将直接数字频率合成器应用于调速，从而实现了对其运动控制部分的要求。     

医院排队叫号系统应用现状综述

为了减少患者在医院的滞留量和高效服务于患者,很多医院都采用了排队叫号系统。医院排队叫号系统产品繁多,医院的实施机制也各不相同,因此分析了目前医院排队叫号系统的应用现状,以及硬、软件实施情况,以求发现系统的主要组成部分和可更新、扩展部分。结合挂号方式、就诊流程优化和物联网技术分析了医院排队叫号系统的发展趋势,这对今后其他领域排队叫号系统的研究有参考意义。     

Concurrent reading while writing revisited

A modification is proposed to Peterson's construction of 1-writern-reader multivalued atomic shared variableusingn+2 multivalued safe variables and some boolean atomic variables. The resulting construction is elegant and is simpler than the original one. K. Vidyasankar received B.E. (Elec. Engg.) from Thiagarajar College of Engineering, Madurai, M. Tech. from I.I.T. Kanpur, India, and Ph.D. in Computer Science from University of Waterloo, Canada. He is now an Associate Professor in Computer Science at Memorial University of Newfoundland, Canada. His research interests include concurrency control and recovery in database systems, concurrency in interprocess communication, design and analysis of algorithms, and graph theory.A prelininary version of this paper, under the title Improving Peterson's Construction of 1-Writern-Reader Multivalued Atomic Register, appears in the Proc. 26th Annual Allerton Conference on Communication, Control, and Computing, University of Illinois at Urbana Champaign, September 1988, pp 693–700