A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.     

3-D MCM封装技术及其应用

介绍了超大规模集成电路（VLSI）用的3-D MCM封装技术的最新发展，重点介绍了3-D MCM封装垂直互连工艺，分析了3-D MCM封装技术的硅效率、复杂程度、热处理、互连密度、系统功率与速度等问题，并对3-D MCM封装的应用作了简要说明。     

Promising alloys for intermediate-temperature solid oxide fuel cell interconnect application

The formation of a low Cr-volatility and electrically conductive oxide outer layer atop an inner chromia layer via thermal oxidation is highly desirable for preventing chromium evaporation from solid oxide fuel cell (SOFC) metallic interconnects at the SOFC operation temperatures. In this paper, a number of ferritic Fe–22Cr alloys with different levels of Mn and Ti as well as a Ni-based alloy Haynes 242 were cyclically oxidized in air at 800 °C for twenty 100-h cycles. No oxide scale spallation was observed during thermal cycling for any of these alloys. A mixed Mn₂O₃/TiO₂ surface layer and/or a (Mn, Cr)₃O₄ spinel outer layer atop a Cr₂O₃ inner layer was formed for the Fe–22Cr series alloys, while an NiO outer layer with a Cr₂O₃ inner layer was developed for Haynes 242 after cyclic oxidation. For the Fe–22Cr series alloys, the effects of Mn and Ti contents as well as alloy purity on the oxidation resistance and scale area specific resistance were evaluated. The performance of the ferritic alloys was compared with that of Haynes 242. The mismatch in thermal expansion coefficient between the different layers in the oxide scale was identified as a potential concern for these otherwise promising alloys.     

低k氟化非晶碳层间介质对芯片性能的影响

讨论了通过合理设计的工艺流程将低k氟化非晶碳材料应用到制造工艺中作为互连介质对集成电路性能的影响。基于一个互连结构简化模型计算出采用低k氟化非晶碳材料作为互连介质后RC延迟、功率耗散和线间串扰的变化情况。采用低k氟化非晶碳介质后,RC延迟和功率耗散随着互连长度的增大而减小,线间串扰也得到显著抑制。     

低功耗电流模互连电路的快速优化设计方法

为对低功耗电流模互连电路进行快速优化,提出了一种"自顶向下"的动态驱动电流模互连电路的快速优化设计方法.方法首先对动态驱动电流模电路进行行为级建模,并采用MATLAB对数据进行处理优化电路功耗,确定出最优的电流源电流大小.然后利用"2ID/gm"方法,快速而准确地确定出相应MOS管尺寸.同时,也对"2ID/gm"的模拟集成电路设计方法,进行了较为详细的理论分析.仿真结果表明:使用该方法确定出的MOS管尺寸得到的性能十分接近设计指标,只需通过少量修改便可完成设计.该方法大大提高了设计效率.     

Virtual and physical address translation mechanism of interconnect network

Most of users are accustomed to utilizing virtual address in their parallel programs running at the scalable high-performance parallel computing systems. Therefore a virtual and physical address translation mechanism is necessary and crucial to bridge the hardware interface and software application. In this paper, a new virtual and physical translation mechanism is proposed, which includes an address validity checker, an address translation cache (ATC), a complete refresh scheme and many reliability designs. The ATC employs a large capacity embedded dynamic random access memory (eDRAM) to meet the high hit ratio requirement. It also can switch the cache and buffer mode to avoid the high latency of accessing the main memory outside. Many tests have been conducted on the real chip, which implements the address translation mechanism. The results show that the ATC has a high hit ratio while running the well-known benchmarks, and additionally demonstrates that the new high-performance mechanism is well designed.     

使用扩展逻辑效力的逻辑路径尺寸优化方法

为解决集成电路物理设计中考虑互连线影响的逻辑路径延迟优化问题,提出一个计入互连线负载的扩展的逻辑效力(ELE),并针对ELE给出一个可同时优化逻辑路径中各个逻辑门尺寸及各段互连线长度的优化流程.ELE在保留原有逻辑效力参数的同时,使用互连寄生参数提取软件获得的Ⅱ型互连线参数,实现对带有互连线负载的逻辑门的传播延迟的描述和估计;逻辑路径优化流程采用效力延迟分配策略作为初始条件来表示各段互连线负载对总效力延迟的影响,将所用目标单元库和制造工艺的物理尺寸信息作为限制条件,以ELE表达式为核心展开优化计算,辅以动态规划办法,无需迭代运算,仅通过一轮计算即可求得全部结果.实验结果表明,该流程计算任务简单,资源耗费少,可以准确、快速地获得所需的逻辑门尺寸和互连线长度;结果清晰合理,与目标单元库和工艺库完全兼容.     

一种用于无线自组网的移动互联协议研究

高效可靠的移动互联协议是高速无线自组织网络移动联网的基础。为解决分层分布式移动自组织网络（HD-MANET）中的传统移动IP协议与实际运用的需求之间存在的矛盾,提出一种移动互联协议。该协议基于抽象分层分布式的网络结构,将移动互联的共性和HD-MANET的特性结合在一起,很好地满足了典型HD-MANET的应用需求。通过OPNET的模拟实验证明,此网络协议大大降低了网络负担,减少了节点连接时的平均时耗。     

PKS+TRICON+PLC结构在神华煤制油过程控制中的应用

PKS+TRICON+PLC结构是神华煤制油过程控制中的主导控制结构。对控制系统组态中如何完善软、硬件的组态,提高煤制油过程控制应用水平进行探讨。     

Noise estimation for deep sub-micron integrated circuits

Noise analysis and avoidance are an increasingly critical step in the design of deep sub-micron (DSM) integrated circuits (ICs). The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs. We introduce an efficient and accurate noise-evaluation method for capacitively coupled nets of ICs. The method holds for a victim net with arbitrary number of aggressive nets under ramp input excitation. For common RC nets extracted by electronic design au-tomation (EDA) tools, the deviation between our method and HSPICE is under 10% .