Dependence of mechanical and tribological performance on the microstructure of (CrAlTiNbV)Nx high-entropy nitride coatings in aviation lubricant

The (CrAlTiNbV)N_x coatings are fabricated by controlling the substrate bias via magnetron sputtering method. Under low substrate bias, the coating tends to form a loose columnar crystal structure with (200) preferred orientation. However, when the substrate bias increases, the coating transforms into a dense nanocrystalline structure, and the (111) orientation is enhanced. As the substrate bias increases, the residual stress and hardness of the coating gradually increase, while the adhesion strength decreases slightly. Friction tests show that the coating possesses the lowest average friction coefficient (about 0.06) and wear rate (8.7 × 10^-9 mm³/N·m) in 4050# aviation lubricant, which is achieved under the substrate bias of -96 V and -126 V, respectively.     

Trypsiligase-Catalyzed Labeling of Proteins on Living Cells

Fluorescent fusion proteins are powerful tools for studying biological processes in living cells, but universal application is limited due to the voluminous size of those tags, which might have an impact on the folding, localization or even the biological function of the target protein. The designed biocatalyst trypsiligase enables site-directed linkage of small-sized fluorescence dyes on the N terminus of integral target proteins located in the outer membrane of living cells through a stable native peptide bond. The function of the approach was tested by using the examples of covalent derivatization of the transmembrane proteins CD147 as well as the EGF receptor, both presented on human HeLa cells. Specific trypsiligase recognition of the site of linkage was mediated by the dipeptide sequence Arg-His added to the proteins’ native N termini, pointing outside the cell membrane. The labeling procedure takes only about 5 minutes, as demonstrated for couplings of the fluorescence dye tetramethyl rhodamine and the affinity label biotin as well.     

Fabrication and joining mechanism of Nano-Cu/Si3N4 ceramic substrates

A novel method for fabricating a nano-Cu/Si₃N₄ ceramic substrate is proposed. The nano-Cu/Si₃N₄ ceramic substrate is first fabricated using spark plasma sintering (SPS) with the addition of nanoscale multilayer films (Ti/TiN/Ti/TiN/Ti) as transition layers. The microstructures of the nano-Cu metal layer and the interface between Cu and Si₃N₄ are investigated. The results show that a higher SPS temperature increases the grain size of the nano-Cu metal layer and affects the hardness. The microstructure of the transition layer evolves significantly after SPS. Ti in the transition layer can react with Si₃N₄ and with nano-Cu to form interfacial reaction layers of TiN and Ti–Cu, respectively; these ensure stronger bonding between nano-Cu and Si₃N₄. Higher SPS temperatures improve the diffusion ability of Ti and Cu, inducing the formation of Ti₃Cu₃O compounds in the nano-Cu metal layer and Ti₂Cu in the transition layer. This study provides an important strategy for designing and constructing a new type of ceramic substrate.     

A Voltage Control Method for a Distributed Line Feeder by means of Multiagent Approach

This paper proposes a method for the coordinated control of power factor by means of a multiagent approach. The proposed multiagent system consists of two types of agent: single feeder agent (F_AG) and bus agent (B_AG). In the proposed system, an F_AG plays as an important role, which decides the power factors of all distributed generators by executing the load flow calculations repeatedly. The voltage control strategies are implemented as the class definition of Java into the system. In order to verify the performance of the proposed method, it has been applied to a typical distribution model system. The simulation results show that the system is able to control very violent fluctuation of the demands and the photovoltaic (PV) generations.     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

Design and performance study of phase‐locked loop using fractional‐order loop filter

The present work reports the realization of an analog fractional‐order phase‐locked loop (FPLL) using a fractional capacitor. The expressions for bandwidth, capture range, and lock range of the FPLL have been derived analytically and then compared with the experimental observations using LM565 IC. It has been observed that bandwidth and capture range can be extended by using FPLL. It has also been found that FPLL can provide faster response and lower phase error at the time of switching compared to its integer‐order counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Three-phase four-wire shunt active power filter based on the SOGI filter and Lyapunov function for DC bus control

The three-phase four-wire shunt active power filter (SAPF) was developed to suppress the harmonic currents generated by nonlinear loads, and for the compensation of unbalanced nonlinear load currents, reactive power, and the harmonic neutral current. In this work, we consider instantaneous reactive power theory (PQ theory) for reference current identification based on the following two algorithms: the classic low-pass filter (LPF) and the second-order generalized integrator (SOGI) filter. Furthermore, since an important process in SAPF control is the regulation of the DC bus voltage at the capacitor, a new controller based on the Lyapunov function is also proposed. A complete simulation of the resultant active filtering system confirms its validity, which uses the SOGI filter to extract the reference currents from the distorted line currents, compared with the traditional PQ theory based on LPF. In addition, the simulation performed also demonstrates the superiority of the proposed approach, for DC bus voltage control based on the Lyapunov function, compared with the traditional proportional-integral (PI) controller. Both novel approaches contribute towards an improvement in the overall performance of the system, which consists of a small rise and settling time, a very low or nonexistent overshoot, and the minimization of the total harmonic distortion (THD).     

Application of differential evolution for cascaded multilevel VSI with harmonics elimination PWM switching

Harmonic elimination pulse width modulation (HEPWM) method has been widely applied to multilevel voltage source inverter (MVSI) to remove low frequency harmonics from its output voltage. However, the computation of the HEPWM switching angles for MVSI is very challenging due to several constraints, namely angle sequencing, very tight angular spacing and the numerous possibilities of angles distribution ratio. Realizing the potential of Differential Evolution (DE) to handle complex problems, this work proposes its application to solve the HEPWM problem for cascaded MVSI. Its emphasis is on improving the availability of HEPWM for higher output voltage by extending the maximum range of modulation index (M). It also removes the discontinuities in the switching angles and reduces the number of distribution ratio required to obtain the required solution. Compared to the most advanced (similar) work, i.e., 7-level MVSI with seventeen switching angles, DE covers a wider range of M; the maximum achievable M is 2.80. Furthermore, it exhibits very low second order distortion factor (DF₂): for the worst case, the value of DF₂ is 0.0014%. To verify the viability of the proposed algorithm, simulation is carried out and hardware prototype is constructed. Both results show very good agreement with the theoretical prediction.