Trajectories of knowledge economy in SSA and MENA countries

In the first critical assessment of knowledge economy dynamic paths in Africa and the Middle East, but for a few exceptions, we find overwhelming support for diminishing cross-country disparities in knowledge-based economy dimensions. The paper employs all the four components of the World Bank's Knowledge Economy Index (KEI): economic incentives, innovation, education, and information infrastructure. The main finding suggests that sub-Saharan African (SSA) and the Middle East and North African (MENA) countries with low levels of KE dynamics and catching-up their counterparts of higher KE levels. We provide the speeds of integration and time necessary to achieve full (100%) integration. Policy implications are also discussed.     

使用FPGA与SDRAM实现液晶显示控制模块的浅析

针对液晶显示控制板上存储器(SRAM)存储量小和频率低的情况,提出了基于DDR sdram作为显示存储器的LCD显示控制器的设计。使用了灵活性与可靠性高的现场可编程门阵列(FPGA)来实现各模块的逻辑功能,分析了实现LCD显示屏控制模块的方案。     

Combined hardware–software multi-parallel prefiltering on the Convey HC-1 for fast homology detection

Protein databases used in research are huge and still grow at a fast pace. Many comparisons need to be done when searching similar (homologous) sequences for a given query sequence in these databases. Comparing a query sequence against all sequences of a huge database using the well-known Smith–Waterman algorithm is very time-consuming. Hidden Markov Models pose an opportunity for reducing the number of entries of a database and also enable to find distantly homologous sequences. Fewer entries are achieved by clustering similar sequences in a Hidden Markov Model. Such an approach is used by the bioinformatics tool HHblits. To further reduce the runtime, HHblits uses two-level prefiltering to reduce the number of time-consuming Viterbi comparisons. Still, prefiltering is very time-consuming. Highly parallel architectures and huge bandwidth are required for processing and transferring the massive amounts of data. In this article, we present an approach exploiting the reconfigurable, hybrid computer architecture Convey HC-1 for migrating the most time-consuming part. The Convey HC-1 with four FPGAs and high memory bandwidth of up to 76.8 GB/s serves as the platform of choice. Other bioinformatics applications have already been successfully supported by the HC-1. Limited by FPGA size only, we present a design that calculates four first-level prefiltering scores per FPGA concurrently, i.e. 16 calculations in total. This score calculation for the query profile against database sequences is done by a modified Smith–Waterman scheme that is internally parallelized 128 times in contrast to the original Streaming ‘Single Instruction Multiple Data (SIMD)’ Extensions (SSE)-supported implementation where only 16-fold parallelism can be exploited and where memory bandwidth poses the limiting factor. Preloading the query profile, we are able to transform the memory-bound implementation to a compute- and resource-bound FPGA design. We tightly integrated the FPGA-based coprocessor into the hybrid computing system by employing task-parallelism for the two-level prefiltering. Despite much lower clock rates, the FPGAs outperform SSE-based execution for the calculation of the prefiltering scores by a factor of 7.9.     

Alloying behavior and novel properties of CoCrFeNiMn high-entropy alloy fabricated by mechanical alloying and spark plasma sintering

An equiatomic CoCrFeNiMn high-entropy alloy was synthesized by mechanical alloying (MA) and spark plasma sintering (SPS). During MA, a solid solution with refined microstructure of 10 nm which consists of a FCC phase and a BCC phase was formed. After SPS consolidation, only one FCC phase can be detected in the HEA bulks. The as-sintered bulks exhibit high compressive strength of 1987 MPa. An interesting magnetic transition associated with the structure coarsening and phase transformation was observed during SPS process.     

The status of and opportunities for utility-scale battery storage in Australia: A regulatory and market perspective

Australia's electricity market is rapidly adding renewable energy generation. Utility-scale batteries could have a major role in facilitating these transitions; however, their deployment is still largely state-subsidized. We summarize the current and future roles for batteries from a legal-economic perspective in the context of Australia's electricity market framework. We find that the future of batteries in Australia is not only a function of the large-scale deployment of renewables, their cost development and the comparative future cost of competing gas turbines but also of national electricity market and state policy reforms focusing on reliability.     

Multi-resource scheduling for FPGA systems

In modern cloud data centers, reconfigurable devices (FPGAs) are used as an alternative to Graphics Processing Units to accelerate data-intensive computations (e.g., machine learning, image and signal processing). Currently, FPGAs are configured to execute fixed workloads, repeatedly over long periods of time. This conflicts with the needs, proper to cloud computing, to flexibly allocate different workloads and to offer the use of physical devices to multiple users. This raises the need for novel, efficient FPGA scheduling algorithms that can decide execution orders close to the optimum in a short time. In this context, we propose a novel scheduling heuristic where groups of tasks that execute together are interposed by hardware reconfigurations. Our contribution is based on gathering tasks around a high-latency task that hides the latency of tasks, within the same group, that run in parallel and have shorter latencies. We evaluated our solution on a benchmark of 37500 random workloads, synthesized from realistic designs (i.e., topology, resource occupancy). For this testbench, on average, our heuristic produces optimum makespan solutions in 47.4% of the cases. It produces acceptable solutions for moderately constrained systems (i.e., the deadline falls within 10% of the optimum makespan) in 90.1% of the cases.     

A scalable architecture for geometric correction of multi-projector display systems

Multi-projector displays allow the realization of large and immersive projection environments by allowing the tiling of projections from multiple projectors. Such tiled displays require real time geometrical warping of the content that is being projected from each projector. This geometrical warping is a computationally intensive operation and is typically applied using high-end graphics processing units (GPUs) that are able to process a defined number of projector channels. Furthermore, this limits the applicability of such multi-projector display systems only to the content that is being generated using desktop based systems. In this paper we propose a platform independent FPGA based scalable hardware architecture for geometric correction of projected content that allows addition of each projector channel at a fractional increase in logic area. The proposed scheme provides real time correction of HD quality video streams and thus enables the use of this technology for embedded and standalone devices.     

继电保护中多路模拟量采集系统的设计

介绍了一种基于高性能浮点DSP芯片TMS320C32、CPLD芯片XC95288和A/D采样芯片AD976组成的多路采集系统的工作原理以及设计方法。通过对第一路施加特殊的电压量,在CCS开发环境下读取采样缓冲区的值,并利用Matlab对采样数据进行了全波傅氏变换。此外,该系统已在继电保护中得到广泛应用,实践表明,该系统能较好地解决多路模拟量的采集,并确保了采样数据的安全可靠性。     

Low-cost and two-cycle hardware structures of PRINCE lightweight block cipher

In this paper, low-cost and two-cycle hardware structures of the PRINCE lightweight block cipher are presented. In the first structure, we proposed an area-constrained structure, and in the second structure, a high-speed implementation of the PRINCE cipher is presented. The substitution box (S-box) and the inverse of S-box (S-box⁻¹) blocks are the most complex blocks in the PRINCE cipher. These blocks are designed by an efficient structure with low critical path delay. In the low-cost structure, the S-boxes and S-boxes⁻¹ are shared between the round computations and the intermediate step of PRINCE cipher. Therefore, the proposed architecture is implemented based on the lowest number of computation resources. The two-cycle implementation of PRINCE cipher is designed by a processing element (PE), which is a general and reconfigurable element. This structure has a regular form with the minimum number of the control signal. Implementation results of the proposed structures in 180-nm CMOS technology and Virtex-4 and Virtex-6 FPGA families are achieved. The proposed structures, based on the results, have better critical path delay and throughput compared with other's related works.