2.4GHz动态CMOS分频器的设计

对现阶段的主流高速CMOS分频器进行分析和比较,在此基础上设计一种采用TSPC(truesingle phase clock)和E-TSPC(extended TSPC)技术的前置双模分频器电路.该分频器大大提高了工作频率,采用0.6μm CMOS工艺参数进行仿真的结果表明,在5V电源电压下,最高频率达到3GHz,功耗仅为8mW.     

理想九点五态控制器原理的叙述

用计算的方式叙述理想九点五态控制器的控制原理。为便于人们理解二阶对象的运动中控制的变化过程,将抽象的对象转换为人们熟知的L-R-C电路,通过调节输入电压(即控制作用)的大小和方向来实现对对象性能的调节,并使系统达到理想的性能指标。最后用仿真来验证计算结果的正确性。     

Reconfigurable hardware implementation of a phase-correlation stereoalgorithm

This paper describes the implementation of a stereo-vision system using Field Programmable Gate Arrays (FPGAs). Reconfigurable hardware, including FPGAs, is an attractive platform for implementing vision algorithms due to its ability to exploit parallelism often found in these algorithms, and due to the speed with which applications can be developed as compared to hardware. The system outputs 8-bit, subpixel disparity estimates for 256× 360 pixel images at 30,fps. A local-weighted phase correlation algorithm for stereo disparity [Fleet, D. J.: {Int. Conf. Syst. Man Cybernetics 1:48–54 (1994)] is implemented. Despite the complexity of performing correlations on multiscale, multiorientation phase data, the system runs as much as 300 times faster in hardware than its software implementation. This paper describes the hardware platform used, the algorithm, and the issues encountered during its hardware implementation. Of particular interest is the implementation of multiscale, steerable filters, which are widely used in computer vision algorithms. Several trade-offs (reducing the number of filter orientations from three to two, using fixed-point computation, changing the location of one localized low-pass filter, and using L1 instead of L2 norms) were required to both fit the design into the available hardware and to achieve video-rate processing. Finally, results from the system are given both for synthetic data sets as well as several standard stereo-pair test images.     

Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic

Currently there are design barriers inhibiting the implementation of high-precision digital signal processing (DSP) objects with field programmable logic (FPL) devices. This paper explores overcoming these barriers by fusing together the popular distributed arithmetic (DA) method with the residue number system (RNS) for use in FPL-centric designs. The new design paradigm is studied in the context of a high-performance filter bank and a discrete wavelet transform (DWT). The proposed design paradigm is facilitated by a new RNS accumulator structure based on a carry save adder (CSA). The reported methodology also introduces a polyphase filter structure that results in a reduced look-up table (LUT) budget. The 2C-DA and RNS-DA are compared, in the context of a FPL implementation strategy, using a discrete wavelet transform (DWT) filter bank as a common design theme. The results show that the RNS-DA, compared to a traditional 2C-DA design, enjoys a performance advantage that increases with precision (wordlength).     

双波长稳频CO_2激光模糊控制系统的建模与优化

报导一种模糊逻辑控制系统的建模与优化方法。以此方法设计的模糊逻辑控制器，用于双波长稳频ＣＯ２激光器的控制得到令人满意的结果。     

Freelance 2000 DCS在轴流机上的应用

简要介绍了Freelance 2000 DCS的功能特点以及轴流机的控制要求.结合轴流机的控制特点，用Freelance 2000 DCS对原模拟电子系统进行改造，实现并改进了轴流机流量－静叶位置调节、防喘振控制、逻辑控制、状态监测、信息管理等功能。改造后的系统可靠性高、技术先进、信息管理功能强，其设计思想和方法均可供石化企业大型压缩机控制系统的设计和改造借鉴。     

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.     

在系统可编程通用数字开关ispGDS14的原理及应用

介绍了Lattice公司生产的在系统可编程通用数字开关芯片ispGDS14的内部结构和性能特点，并通过实例说明了在GDS开发环境下对ispGDS14进行编程的方法。     

The formalization and analysis of a communications protocol

The MSMIE protocol [SBC89] allows processors in a distributed system to communicate via shared memory. It was designed to meet the reliability and efficiency needs of applications such as nuclear safety systems. We present a formal model of the MSMIE protocol expressed in the notation CCS. Desirable properties of the protocol are expressed in the modal mu-calculus, an expressive modal logic. We show that the protocol lacks an important liveness property. In actual operation, additional operating constraints are checked to avoid potential problems. We present a modified protocol and show that it possesses the liveness property even without checking operating constraints. We also show how parts of the analysis were automated with the Concurrency Workbench.     

A genetic‐based neuro‐fuzzy controller for blind equalization of time‐varying channels

This paper presents a neuro‐fuzzy network (NFN) where all its parameters can be tuned simultaneously using genetic algorithms (GAs). The approach combines the merits of fuzzy logic theory, neural networks and GAs. The proposed NFN does not require a priori knowledge about the system and eliminates the need for complicated design steps such as manual tuning of input–output membership functions, and selection of fuzzy rule base. Although, only conventional GAs have been used, convergence results are very encouraging. A well‐known numerical example derived from literature is used to evaluate and compare the performance of the network with other equalizing approaches. Simulation results show that the proposed neuro‐fuzzy controller, all parameters of which have been tuned simultaneously using GAs, offers advantages over existing equalizers and has improved performance. From the perspective of application and implementation, this paper is very interesting as it provides a new method for performing blind equalization. The main contribution of this paper is the use of learning algorithms to train a feed‐forward neural network for M‐ary QAM and PSK signals. This paper also provides a platform for researchers of the area for further development. Copyright © 2008 John Wiley & Sons, Ltd.