Analysis and Simulation of S-shaped Waveguide in Silicon-on-insulator

The simulation and analysis of S-shaped waveguide bend are presented.Bend radius larger than 30 mm assures less than 0.5 dB radiation loss for a 4-μm-wide silicon-on-insulator waveguide bend with 2-μm etch depth.Intersection angle greater than 20° provides negligible crosstalk (<-30 dB) and very low insertion loss.Any reduction in bend radius and intersection angle is at the cost of the degradation of characteristics of bent waveguide and intersecting waveguide, respectively.     

Stress reduction in GaN films on (111) silicon-on-insulator substrate grown by metal-organic chemical vapor deposition

The GaN film was grown on the (111) silicon-on-insulator (SOI) substrate by metal-organic chemical vapor deposition and then annealed in the deposition chamber. A multiple beam optical stress sensor was used for the in-situ stress measurement, and X-ray diffraction (XRD) and Raman spectroscopy were used for the characterization of GaN film. Comparing the characterization results of the GaN films on the bulk silicon and SOI substrates, we can see that the Raman spectra show the 3.0 cm^− 1 frequency shift of E₂(TO), and the full width at half maximum of XRD rocking curves for GaN (0002) decrease from 954 arc sec to 472 arc sec. The results show that the SOI substrates can reduce the tensile stress in the GaN film and improve the crystalline quality. The annealing process is helpful for the stress reduction of the GaN film. The SOI substrate with the thin top silicon film is more effective than the thick top silicon film SOI substrate for the stress reduction.     

Dopant segregation in SOI Schottky-barrier MOSFETs

We present experimental results on silicon-on-insulator Schottky-barrier MOSFETs with fully silicided NiSi source and drain contacts. Dopant segregation during silicidation was used to improve the device characteristics: on-currents, significantly higher than without dopant segregation as well as an almost ideal off-state are demonstrated in n-type as well as p-type SB-MOSFETs. Temperature dependent measurements show that the effective Schottky-barrier height in devices with segregation can be strongly lowered. In addition, we investigate the dopant segregation technique with simulations. Comparing simulations with experiments it turns out that the spatial extend of the segregation layer is on the few nanometer scale which is necessary for ultimately scaled devices. Furthermore, the use of ultrathin-body SOI in combination with ultrathin gate oxides results in an even further increased transmission through the Schottky barriers and consequently leads to strongly improved device characteristics. As a result, the dopant segregation technique greatly relaxes the requirement of low Schottky-barrier silicides for high performance transistor devices.     

SOI集成电路的ESD保护技术研究进展

近年来，随着SOI技术的快速发展，SOI集成电路的ESD保护已成为一个主要的可靠性设计问题。介绍了SOI ESD保护器件方面的最新进展，阐述了在SOI ESD保护器件设计和优化中出现的新问题，并进行了详细的讨论。     

Materials study of silicon-on-lnsulator material by TEM

Silicon-on-insulator (SOI) technology addresses the need for many different device applications, such as radiation tolerant devices, high voltage, and three-dimensional circuitry applications. Isolated silicon epitaxy (ISE) is a commercialised process which results in excellent SOI material quality with proven results, having overcome most of the obstacles of other processes, although only having reduced, not eliminated, threading dislocations. The remaining isolated dislocations have been examined in detail by transmission electron microscopy (TEM). These have been diagnosed as normal lattice dislocations, with no faults or twins in the material. The nature, source, and behavior of the remaining dislocations is discussed.     

Thin-film silicon-on-sapphire LDMOS structures for RF power amplifier applications

This work is addressed to the investigation of the electro-thermal performance of RF-LDMOS transistors integrated in TF-SOI, TF-SOS and thinned TF-SOS substrates by means of numerical simulations. Reported experimental trap density, carrier mobility and capture cross-section values have been used together with sapphire datasheet thermal properties, in order to provide accurate simulation results. It is found that subthreshold characteristics are the same for all the analysed substrates while blocking-state, on-state and power dissipation process depends on the substrate type.     

Improving bulk FinFET DC performance in comparison to SOI FinFET

The implementation of FinFET structure in bulk silicon wafers is very attractive due to low-cost technology and compatibility with standard bulk CMOS in comparison with silicon-on-insulator (SOI) FinFET. SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator. We have shown that bulk FinFET with source/drain-to-body (S/D) junctions shallower than gate-bottom has equal or better subthreshold performance than SOI FinFET. By reducing S/D junction depth, fin width scaling for suppression of short-channel-effects (SCEs) can be relaxed. On-state performance has also been examined and drain current difference between the SOI and bulk FinFET at higher body doping levels has been explained by investigating enhanced conduction in silicon-oxide interface corners. By keeping the body doping low and junctions shallower than the gate-bottom, bulk FinFET characteristics can be improved with no increase in process complexity and cost.     

The effect of de-ionized water rinsing after immersion in hydrofluoric acid on the electrical conductivity of silicon nanomembranes

Electrical conductivity of 28 and 220-nm thick silicon membranes was measured by the van der Pauw method in dry air (relative humidity < 5%) at room temperature (around 20 °C). Immediately after hydrofluoric acid immersion the conductivity increases several orders of magnitude because of surface-induced band bending; it then drops and reaches the level of samples with a native oxide surface in several weeks due to the surface's re-oxidation. The oxidation rate is found to increase with the de-ionized water rinsing time, which is confirmed by X-ray photo electron spectroscopy measurements.     

Silicon orientation effects on surface blistering characteristics due to hydrogen ion implantation

This study attempted to examine surface blistering characteristics induced by room-temperature implantation of 5 × 10¹⁶ cm^− 2 40 keV hydrogen ions into Si<111> wafers followed by furnace annealing treatments at various temperatures for a duration of 1 h. The results obtained in our previous work [1], in which Si<100> wafers were used, were adopted for making comparisons. A comparison of Si<111> and Si<100> resulted in blister distributions with greater areal number densities, smaller diameters, similar covered-area fractions, higher threshold and saturation post-annealing temperatures, larger apparent activation energy levels, smaller hydrogen-trapping and oxygen-gettering depths, higher threshold post-annealing temperatures for hydrogen trapping and oxygen gettering, and lower SIMS peak intensities at hydrogen-trapping and oxygen-gettering depths. Furthermore, the K values for Si<111> were less than those for Si<100> when post-annealing temperatures ranged from 200 to 450 °C. Conversely, just the opposite was true when post-annealing temperatures ranged from 450 to 550 °C. In addition, the crater distributions achieved in Si<111> had lower areal number densities and covered-area fractions, higher threshold and saturation post-annealing temperatures, and smaller crater depths compared to Si<100>. In both Si<111> and Si<100>, areal number densities and covered-area fractions in the crater distributions were lower than those in the blister distributions.     

基于0.18μm工艺SOI技术60V LDNMOS的设计与分析

随着功率器件尺寸的不断缩小,绝缘体上硅技术所受的关注度日益增加。在0.18μm工艺条件下基于SOI技术,运用SILVACO公司的Athena工艺仿真和Atlas器件仿真模拟软件,研究分析一种了60V LDNMOS结构,对不同沟道管宽度的器件进行设计和分析,并结合实际流片的测试结果,对器件直流性能进行了表征与分析,发现SOI器件无明显的由氧化埋层隔离作用所产生的显著影响器件性能的浮体效应和kink 效应,实现了性能优良的小尺寸60V LDNMOS器件。