基于IEEE1149.4的测试方法研究

根据混合信号边界扫描测试的工作机制，提出了符合l149．4标准的测试方法，并用本研究室开发的混合信号边界扫描测试系统进行了测试验证。     

Methods of Testing Discrete Semiconductors in the 1149.4 Environment

This paper describes measurement methods for testing discrete semiconductors in the environment defined by the IEEE 1149.4 standard for a mixed-signal bus. First, the paper introduces and illustrates measurement procedures for obtaining such essential electrical parameters of diodes and transistors as can be used for testing and identification. Then, the procedures are carried out and the achieved measurement results presented. To demonstrate the usability of the measurement procedures, the paper then presents test methods and measurement results for discrete component blocks. The results indicate that testing and measuring some of the electrical parameters of discrete semiconductors is possible in the 1149.4 environment. These parameters allow the determination of whether the component under test is working properly or not. Our tests only covered the semiconductors’ DC features, disregarding their AC features. Also discussed are limitations of the 1149.4 environment in discrete semiconductor testing.

模拟集成电路的边界扫描可测性设计方案

提出了一种基于边界扫描技术的模拟集成电路内建自测试方案。该方案依照IEEE 1149.4边界扫描测试标准, 在添加极少电路元件的基础上, 增加了电路性能测试单元(FTM), 能够充分利用电路系统中已有数模混合资源, 通过控制器内部向被测电路施加激励, 完成模拟集成电路的功能性测试。采用Cyclone II系列芯片EP2C35F672C8实现测试系统设计, 并以模拟集成滤波芯片MAX292为被测核心电路展开实验, 其频率特性的测试结果表明了该测试方案的正确性和系统测试的有效性。     

IEEE 1149.4标准实验测试结构设计和扩展研究

本文采用复杂可编程逻辑器件（CPLD）和分立器件,设计实现了IEEE 1149.4混合信号边界扫描标准实验测试结构。为了提高互连测试的故障诊断能力,文中对模拟边界模块（ABM）开关结构进行了一些修改。针对ABM单元的这些修改允许测试者可以将模拟输入信号与多个电压进行比较。当测试者在简单互连或扩展互连中遇到桥接故障,扩展的ABM开关结构使得故障更容易探测。     

混合信号集成电路边界扫描测试技术的实现

IEEE1149.4为混合信号的测试提供了一项标准,同时也提供了一种重要的可测试性设计（DFT）技术,该技术不仅可以测试芯片或PCB之间的管脚连接是否存在故障,还可以测试芯片的逻辑功能。本文以IEEE1149.4标准为基础,结合混合信号边界扫描测试系统进行了测试验证,完成对混合信号电路的参数测试。     

A prognostic method for the embedded failure monitoring of solder interconnections with 1149.4 test bus architecture

This paper describes the feasibility of accurate low frequency measurements in predicting the breakdown of modern lead free ball grid array (BGA) interconnections. In these measurements, performed partly with 1149.4 analogue boundary scan, ceramic BGA modules measuring 15×15 mm in width, with 9×9 ball matrixes, were attached on an FR-4 printed wiring board (PWB) and thermally cycled over a temperature range of −40 to +125 °C. The condition of corner interconnections was monitored using the developed measurement methods and construction. In-situ measurements were performed with a datalogger during temperature cycling, accompanied with 1149.4 mixed-signal test bus measurements of corner interconnections performed between cycling intervals. In addition, the measurements were complemented by scanning acoustic microscopy and, X-ray. Monitoring corner interconnections by a simple, low-frequency voltage measurement method with embedded test constructions gives an early warning indication well before the electrical interconnection failures. Of two studied interconnection compositions, the ones with plastic core solder balls (PCSB) proved to be more reliable than the ones with 90/10 PbSn balls.     

从边界扫描技术协议讨论其发展与应用

边界扫描测试技术作为当前电子测试技术的热点,其应用与发展是令人瞩目的。本文通过对边界扫描技术一系列协议的简单介绍和剖析,讨论了边界扫描技术各个阶段的应用与发展情况,并对边界扫描技术未来的发展给出了一些预测。     

IEEE1149.4模拟和混合信号测试总线标准

模拟和混合信号边界扫描标准(IEEE1149.4)是针对电路板级外部分立元件的测试而发展起来的,该标准与IEEE1149.1兼容,另外,在此基础上,IEEE1149.4又增加了两根线,用来控制模拟信号.目前1149.4的标准,不但应用在传统的电路板上,在混合信号集成电路甚至包含混合信号的SoC系统芯片上,都有应用.本文...     

基于IEEE 1149.4标准的参数测试系统的设计

为了实现对混合信号电路的参数测试,本文提出一种以FPGA为主控器的基于IEEE 1149.4标准的参数测试系统。实验结果表明,该系统符合IEEE 1149.4标准的基本要求,测试准确。该测试系统的设计为IEEE 1149.4标准提供了一种实现方法,可扩展性强,为更好的解决混合电路测试打下了良好的基础。     

SOC混合信号测试难题的解决策略

缺乏可控制性和可观察性是SOC嵌入式内核测试电路最难解决的问题.本文提出在SOC嵌入式内核测试电路中引入DFT和BIST方法.介绍了IEEE1149.4混合信号测试总线及其应用特点,讨论运用重配置的DFT方法和测试点插入的DFT方法来增强混合信号系统的可控制性和可观察性.阐述ADC/DAC与PLL两种电路的BIST技术在SOC嵌入式内核测试的应用.为解决SOC混合信号测试难题提供一种有效的方法.