快速二进制补码平方运算算法及结构

针对二进制补码平方运算的特点，提出了一种快速实现算法，即利用专用集成电路设计中的标准单元库中低位乘法（平方）构件或通过其他算法实现的模块，并经部分积重组而形成更少的部分积，行数仅5行，与闰方位宽无关，极大地缩短了加法阵列的计算时间，同时在一定程度上减少了系统所用资源。     

An efficient hardware implementation of the elliptic curve cryptographic processor over prime field,

Elliptic curve cryptography (ECC) schemes are widely adopted for the digital signature applications due to their key sizes, hardware resources, and higher security per bit than Rivest-Shamir-Adleman (RSA). In this work, we proposed a new hardware architecture for elliptic curve scalar multiplication (ECSM) in Jacobian coordinates over prime field, . This is a combination of point doubling and point addition architecture, implemented using resource sharing concept to achieve high speed and low hardware resources, which is synthesized both in field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC). The proposed ECSM takes 1.76 and 2.44 ms on Virtex-7 FPGA platform over 224-bit and 256-bit prime field, respectively. Similarly, ASIC (GF 40 nm complementary metal-oxide semiconductor [CMOS]) technology implementation provides energy efficient with a latency of 0.46 and 0.6 ms over prime field and , respectively. This design provides better area-delay product and high throughput value in both FPGA and ASIC when compared with other designs.     

基于PROFIBUS-PA通信接口的智能电磁流量计设计

针对工业控制系统的特点和要求,设计并实现了具有PROFIBUS-PA通信功能的电磁流量计,使用了新型专用通信接口芯片SPC4和SIM1-2,构成了PROFIBUS-PA总线中的一个智能从站。文中给出了PROFIBUS-PA部分的主要硬件设计框图及软件流程图,实现了低价位开发从站的目的。     

Hot wire chemical vapor processing (HWCVP) — A prospective tool for VLSI

Today the Very Large Scale Industry (VLSI) is looking towards process solutions, which will avoid the problems associated with the conventional or presently employed technologies. This demand has become more intense with the VLSI industry extending their horizons towards Micro electro-mechanical systems (MEMS) based devices and Application-Specific Integrated Circuits ASICs). The areas of concern are development of high-k dielectric thin films, highly conducting polysilicon thin films, ultra thin diffusion barriers on low dielectric constant layers with electromigration resistant metal interconnects. Over the last few years, work carried out on the hot wire chemical vapor process (HWCVP) has shown that, this technique has great potential to yield the desired materials at low processing temperatures. This paper discusses the results we have obtained in the above areas and also the extension of application of this technique to areas like MEMS and ASICs.     

siRNA沉默ASIC1a基因对佐剂性关节炎大鼠关节软骨细胞凋亡的影响研究

目的: 探讨小分子干扰RNA(siRNA)技术诱导佐剂性关节炎(adjuvant-induced arthritis,AA)大鼠关节软骨细胞中ASIC1a表达沉默对细胞凋亡的影响。方法: 通过化学合成法合成特异性荧光短链ASIC1a siRNA-FAM,使用Lipofectamine 2000转染试剂盒将ASIC1a siRNA转染入关节软骨细胞,采用荧光显微镜、流式细胞术、实时荧光定量PCR(q-RT-PCR)及Western Blot法检测siRNA转染效率及其对ASIC1a mRNA和蛋白表达的抑制作用。同时采用Annexin-V /PI流式细胞术检测各组细胞凋亡情况。结果: ASIC1a siRNA能成功转入软骨细胞,转染后AA大鼠关节软骨细胞中ASIC1a mRNA表达显著低于对照组 (P<0.01),最大抑制率为85.4 %;Western Blot结果显示,转染特异性siRNA后ASIC1a蛋白表达明显低于对照组(P<0.01)。Annexin-V /PI流式细胞术结果表明,与模型组相比,siRNA-3转染引起ASIC1a表达沉默后AA大鼠软骨细胞凋亡明显减少。结论: siRNA介导的AA大鼠关节软骨细胞ASIC1a表达沉默模型是研究酸敏感离子通道对软骨细胞代谢影响的可靠模型,siRNA-3转染对胞外酸化刺激条件下AA大鼠关节软骨细胞凋亡的保护作用可能与其调节ASIC1a的表达有关。     

Clock gating methodologies and tools: a survey

Clock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits. Although it is a mature technique, theoretical work and tools for its application are still evolving and considered a matter of ongoing research, due to its significant effect in the overall power of the designs under study. This paper introduces a detailed review of the spectrum of CG approaches, theoretical and practical, from an architectural and register transfer level to synthesis, place and route, and testing issues. Furthermore, tools availability, limitations, and requirements concerning CG are examined for each design flow step. Conclusively, an evaluation of the presented techniques and literature is provided, estimating their usefulness and identifying areas for future research, exploration, and automation. Copyright © 2015 John Wiley & Sons, Ltd.     

Reliability Model for Polyimide–Metal Interconnect Shorts in GaAs ASICs

A physical reliability model has been developed to calculate the time to failure of polyimide–metal multilevel interconnected GaAs components due to the shorts between interconnect metallizations through a polyimide interlayer. The failure mechanism for the shorts between neighboring metals through the polyimide is described as a stress‐assisted diffusion process along a polyimide microcrack due to the combination of process defect and high thermal stress concentration. The finite element method has been used to determine the temperature increase during operation and the resulting thermal stress due to the difference in coefficients of thermal expansion (CTEs) of the materials used in the multilevel metallization GaAs module of devices. Numerical methods have been used to solve the partial differential diffusion equations with stress gradients in order to obtain the time to failure of the devices. The time to failure for the shorts between metal level 4 and metal 2 at 123 °C operating temperature was calculated to be 20 h for the conditions analyzed. The activation energy for the failure of the shorts between two level metals was calculated to be 0.48 eV. Copyright © 2004 John Wiley & Sons, Ltd.     

一种面向数学解算的专用处理器设计方案与实现

本文针对数字信号处理，工业控制等领域中出现的数学解算及其高速和实时性的要求，提出了一种专用处理器的设计方案。并且实现了这种专用处理器。该处理器具有特别的精简指令系统，指令流和数据流分离的结构，微码控制方式，高速乘加运算部件，多寄存器堆，嵌入式协处理工作方式，可微编程序等技术特点。另外，这种处理器还具有高的性能价格比。     

Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality

The computational power required in many multimedia applications is well beyond the capabilities of today's multimedia systems. Therefore, the embedding of additional high-performance accelerator multimedia components into these systems is most decisive. This paper presents the embedding of multimedia components into computer systems using reconfigurable coprocessor boards. The goal of those reconfigurable platforms which can be adapted to several applications and which include programmable digital signal processors, control and memory devices as well as dedicated multimedia ASICs is worked out. On the way to such a platform four ASICs for image and text processing are presented. The embedding of these components into a computing system using a CardBus-based coprocessor board is shown. Such a reconfigurable coprocessor board is an important intermediate stage on the way to future hybrid reconfigurable systems on chip.     

The off-detector opto-electronics for the optical links of the ATLAS Semiconductor Tracker and Pixel detector

The off-detector part of the optical links for the ATLAS SCT and Pixel detectors is described. The VCSELs and p–i–n diodes used and the associated ASICs are described. A novel array packaging technique is explained and an analysis of the performance of the arrays and the overall system performance is given. The proposed procedure for the set-up of the optical links in ATLAS is described.