一种高速浮点加法器的设计实现

浮点加法器是协处理器的核心运算部件，是实现浮点指令各种运算的基础，其设计优化是提高浮点运算速度和精度的关键途径。文章从浮点加法器算法和电路实现的角度给出设计方法，并且提出动态与静态结合设计进位链的方案以及前导O预测面积与速度的折衷方法。动态与静态结合设计进位链的方法有效地降低了功耗，提高了速度，改善了性能。目前已经嵌入协处理器的设计中，并且流片测试成功。     

反转矢量透射反馈求解光电混合全加器

提出了利用反转矢量透射反馈算法研制偏振编码光电混合全加器，该加法器可以实现两输入的光学算术运算，研制成的各单元器件可用于其它各种光计算机系统中。     

加法器在锅炉汽包水位控制系统中的应用

介绍了蒸汽锅炉水位控制系统中如何应用一个加法器，实现当主汽流量变化较大时，给水流量跟踪主汽流量来达到控制汽包水位目的的一种控制方法。     

A novel design of 8-bit adder/subtractor by quantum-dot cellular automata

Application of quantum-dot is a promising technology for implementing digital systems at nano-scale. QCA supports the new devices with nanotechnology architecture. This technique works based on electron interactions inside quantum-dots leading to emergence of quantum features and decreasing the problem of future integrated circuits in terms of size. In this paper, we will successfully design, implement and simulate a new full adder based on QCA with the minimum delay, area and complexities. Also, new XOR gates will be presented which are used in 8-bit controllable inverter in QCA. Furthermore, a new 8-bit full adder is designed based on the majority gate in the QCA, with the minimum number of cells and area which combines both designs to implement an 8-bit adder/subtractor in the QCA. This 8-bit adder/subtractor circuit has the minimum delay and complexity. Being potentially pipeline, the QCA technology calculates the maximum operating speed.     

基于CORDIC算法的高速正余弦函数实现架构

坐标旋转数字计算机算法（Coordinates Rotation Digital Computer （CORDIC） Algorithm）,其硬件结构实现简单,可以在硬件系统中实现包括乘、除、各种三角函数、自然对数和平方根在内的初等函数;针对图像处理对计算速度要求高的特点,本文采用了多级流水线的实现架构,可以明显提高CORDIC电路的工作频率;为了进一步地减少各级流水线的计算时延,电路中采用了运算速度较快的BKA加法器。基于Altera公司的FPGA（EP2C5F256C7）芯片的CORDIC算法架构综合,使其能够工作在188．38MHz的最高时钟频率。仿真结果表明本文提出的CORDIC架构能高速正确地实现CORDIC算法。     

一种Ling选择进位加法器

设计一种Ling选择进位加法器,组间采用Ling进位代替传统的进位,利用内部连线与节点扇出平衡的并行前缀逻辑产生进位机制,并对通常的进位选择模块进行调整,以使其适合Ling进位。该加法器兼具了Ling加法器的快速性,又避免了逻辑产生的复杂性。实验结果表明,与超前进位加法器相比,该加法器的速度提高12％左右。     

Arithmetic computation in the tile assembly model: Addition and multiplication

Formalized study of self-assembly has led to the definition of the tile assembly model [Erik Winfree, Algorithmic self-assembly of DNA, Ph.D. Thesis, Caltech, Pasadena, CA, June 1998; Paul Rothemund, Erik Winfree, The program-size complexity of self-assembled squares, in: ACM Symposium on Theory of Computing, STOC02, Montreal, Quebec, Canada, 2001, pp. 459–468]. Research has identified two issues at the heart of self-assembling systems: the number of steps it takes for an assembly to complete, assuming maximum parallelism, and the minimal number of tiles necessary to assemble a shape. In this paper, I define the notion of a tile assembly system that computes a function, and tackle these issues for systems that compute the sum and product of two numbers. I demonstrate constructions of such systems with optimal Θ(1)$\Theta \left(1\right)$ distinct tile types and prove the assembly time is linear in the size of the input.     

基于模块化结构的N位加法器的测试生成

针对单个ｓｔｕｃｋ－ａｔ故障，研究了Ｎ位加法器的测试矢量生成问题，对于行波进位加法器，只需８个测试矢量就可得到１００％的故障覆盖率；对于Ｎ位先行进位加法器，只需Ｎ＾２＋２Ｎ＋３个测试矢量即可得到１００％的故障覆盖率。     

光电积累检测原理和发现概率及虚警概率的测试方法

本文从理论上分别研究噪声和信号加噪声通过选频电路的统计特性,根据两者的差别,提出了抑制噪声的抗干扰电路。叙述积累检测原理及检测电路,并从理论上分析积累检测对检测性能的贡献,进而介绍光电检测中发现概率和虚警概率的测试方法。     

双进位五输入加法器及其应用

本文提出了一种处理信息量较大的双进位五输入加法器模块。通过九输入加法器及三数相加的串行进位加法器等设计实例证明了它能减少在运算电路中加法器模块的使用数量。