Effect of epitaxial realignment on the leakage behavior of arsenic-implanted,as-deposited polycrystalline Si-on-single crystal Si diodes

When dopants are indiffused from a heavily implanted polycrystalline silicon film deposited on a silicon substrate, high thermal budget annealing can cause the interfacial “native” oxide at the polycrystalline silicon-single crystal silicon interface to break up into oxide clusters, causing epitaxial realignment of the polycrystalline silicon layer with respect to the silicon substrate. Anomalous transient enhanced diffusion occurs during epitaxial realignment and this has adverse effects on the leakage characteristics of the shallow junctions formed in the silicon substrate using this technique. The degradation in the leakage current is mainly due to increased generation-recombination in the depletion region because of defect injection from the interface.     

场效应管及其放大电路教学方法研究

场效应管及其放大电路是模拟电子技术教学难点之一,传统的教学往往效果欠佳。场效应管和三极管都是半导体放大器件,二者有很多相似之处,在学习了三极管及其放大电路之后,运用比较的方法对场效应管及其放大电路进行教学,可以温故而知新,找到两者之间的异同点,提高学习兴趣和效率,达到事半功倍的效果。     

High power devices in wide bandgap semiconductors

Silicon carbide (SiC) semiconductor devices for high power applications are now commercially available as discrete devices. Recently Schottky diodes are offered by both USA and Europe based companies. Active switching devices such as bipolar junction transistors (BJTs), field effect transistors (JFETs and MOSFETs) are now reaching the market. The interest is rapidly growing for these devices in high power and high temperature applications. The main advantages of wide bandgap semiconductors are their very hi...     

Physical phenomena affecting performance and reliability of 4H-SiC bipolar junction transistors

The silicon carbide bipolar junction transistor (BJT) is attractive for use in high-voltage switching applications offering high-voltage blocking characteristics, low switching losses, and is capable of operating at current densities exceeding 300 A/cm². However, performance reliability issues such as degradation of current gain and on-resistance currently prohibit commercial production of 4H-SiC BJTs. This paper examines the physical mechanisms responsible for this degradation as well as the impact that these physical phenomena have on device performance. Results were obtained through the examination of several types of N-P-N BJT structures using various fabrication methodologies. Electron-beam induced current (EBIC) and potassium hydroxide (KOH) etching were used to characterize defect content in the material, before and after device current stress, when possible. It was found that Shockley stacking faults (stress-induced structures) associated with the forward voltage drift phenomenon in SiC bipolar diodes, also play a major role in the reduction of gain and an increase of on-resistance of the BJTs. However, results from some devices suggest that additional processes at the device periphery (edge of the emitter) may also contribute to degradation in electrical performance. Hence, it is essential that the sources of electrical degradation, identified in this paper, be eliminated for SiC BJTs to be viable for commercial scale production.     

Proportional BIC sensor for current testing

A new design of a BIC sensor for current testing static CMOS circuits is proposed. It is based on a lateral BJT device which is easy to incorporate in any standard CMOS process. The design diverts a fraction of the I _DDQ current from the cell under test and a resistive component generates a voltage proportional to I _DDQ . Additional features are the possibility of continuous measure of i _dd and increased speed of this sensor compared with sensors based on the current integration principle. The design does not have substrate currents due to the parasitic vertical BJTs. Experimental work on the sensor is reported.     

Revisited generalized substitution theorem and its consequences for circuit analysis

The Substitution Theorem (ST) is generally perceived as a mere theoretical curiosity. In this paper, a formerly derived generalized ST (GST) is carefully revised, which leads to both a Weak Revisited GST (RGST) and a Strong RGST (characterized by noticeably relaxed hypotheses with respect to the GST). Then, despite the common opinion about the ST, such RGSTs are showed to be powerful analytical tools to generalize, make rigorous and rigorously prove several classic results of Circuit Theory, namely: the Substitution Theorem for Multiterminal Circuits, the Source‐Shift Theorem, the Thévenin–Norton Theorem, the Miller Theorem alongside its Dual, and the Augmentation Principle. More specifically, the Substitution Theorem for Multiterminal Circuits is extended to an arbitrary set of sources, possibly including nullors. The Source‐Shift Theorem is rigorously derived, and possible related ambiguities are removed. Also, all possible hybrid forms of the Thévenin–Norton Theorem for multiports are individuated, and a precise operative procedure for calculating the relevant entities is provided for all cases. Furthermore, the Miller Theorem and its Dual are extended to an arbitrary number of variables and to multiports. As to the Augmentation Principle, the constraint regarding the linearity of the augmenting resistors is removed. Finally, thoroughly worked examples are given in which the aforementioned noteworthy consequences of the RGSTs are proved to be efficient tools for analysis by inspection of linear and nonlinear circuits. Among the other things, systematic pencil‐and‐paper procedures for DC‐point and input‐output (or driving‐point) characteristic calculation in nonlinear networks are derived and applied to circuits with considerably complex topology. Copyright © 2016 John Wiley & Sons, Ltd.     

一种新式SEU加固PD SOI SRAM单元

本文提出了一种新式SEU加固的10管PD SOI静态存储单元。通过将互锁反相器中的上拉和下拉管分割成两个串联的晶体管,该单元可有效抑制PD SOI晶体管中的寄生BJT和源漏穿通电荷收集效应,这两种电荷收集效应是引起PD SOISRAM翻转的主要原因。通过混合仿真发现,与穿通的浮体6T单元相比,该单元可完全解决粒子入射单个晶体管引起的单粒子翻转。通过分析该新式单元的翻转机制,认为其SEU性能近似与6T SOI SRAM的单粒子多位翻转性能相等。根据参考文献的测试数据,粗略估计该新式单元的SEU性能比普通45nm 6T SOI SRAM单元提升了17倍。由于新增加了四个晶体管,该单元在面积上增加了43.4%的开销,性能方面有所降低。     

Understanding the failure mechanisms of microwave bipolar transistors caused by electrostatic discharge

Electrostatic discharge(ESD) phenomena involve both electrical and thermal effects,and a direct electrostatic discharge to an electronic device is one of the most severe threats to component reliability.Therefore, the electrical and thermal stability of multifinger microwave bipolar transistors(BJTs) under ESD conditions has been investigated theoretically and experimentally.100 samples have been tested for multiple pulses until a failure occurred.Meanwhile,the distributions of electric field,current density and lattice temperature have also been analyzed by use of the two-dimensional device simulation tool Medici.There is a good agreement between the simulated results and failure analysis.In the case of a thermal couple,the avalanche current distribution in the fingers is in general spatially unstable and results in the formation of current crowding effects and crystal defects.The experimental results indicate that a collector-base junction is more sensitive to ESD than an emitter-base junction based on the special device structure.When the ESD level increased to 1.3 kV,the collector-base junction has been burnt out first.The analysis has also demonstrated that ESD failures occur generally by upsetting the breakdown voltage of the dielectric or overheating of the aluminum-silicon eutectic.In addition,fatigue phenomena are observed during ESD testing,with devices that still function after repeated low-intensity ESDs but whose performances have been severely degraded.     

低电压高效率微波功率放大器研究与设计

介绍了一种应用于低电压的微波双极性晶体管放大器的电路设计方法。通过分析微波晶体管的模型,比较了小信号法、负载牵引法和文中使用匹配方法对输出功率、效率和线性度的影响。文中设计了一款可以用于GSM通信终端发射的功率放大器,并对采用3种不同匹配方式进行对比,仿真结果表明,文中所用方法输出功率和效率较高、线性度较好。     

低噪声高单位增益带宽双极型运放设计

设计了一款低噪声、高单位增益带宽的运放电路。该款电路基于0.25μm SiGe双极工艺,采用三级级联的形式,输入级选取多个双极型晶体管(BJT)并联,用作差分对管,以抑制噪声;中间级不但用pnp型BJT镜像电流源作为有源负载,而且并联多个横向pnp型BJT用以提升单位增益带宽;输出级则设计成低电容输入和低电容输出方式,借此拓展带宽。对所设计的运放电路进行了PSPICE仿真及硬件电路实验。结果表明,当电源电压为2.5 V时,运放电路的实测交流开环电压增益为80 dB,开环相位裕度为61.5°,单位增益带宽为203 MHz,在10 kHz处的输入电压噪声密度仅为1.2 nV/Hz~(1/Hz),因而可用于低噪声、高单位增益带宽的片上相位噪声测量电路和微波功率传感器等系统的设计中。