Electrical properties of (Bi3.5La0.5)Ti3O12 thin-films prepared by liquid source misted chemical deposition

The ((Bi_3.5La_0.5)Ti₃O₁₂(BLT) thin-films used in this study were fabricated on a Pt(111)/SiO₂/Si(100) substrate by a Liquid Source Misted Chemical Deposition (LSMCD) technique. X-ray diffraction patterns showed that the BLT films were crystallized and no other phases were observed when annealed above 650 ‡C. Grain size and remnant polarizations increased with increase in the annealing temperature, while leakage current densities decreased. The remnant polarizations (Pr) increased from 2.0 to 4.8 and 19.0 μC/cm2 with increase in the annealing temperature from 650 to 700 and 750 ‡C, respectively. The BLT films annealed at 700 ‡C in O₂ showed a good fatigue resistance of reduced polarization by 10% after 10⁹ switching cycles when 9 V of bipolar voltage was applied at a frequency of 40 kHz.     

电磁拓扑分析中的BLT方程及其应用

文章论述了分析复杂系统的电磁干扰问题的电磁拓扑方法，主要介绍了电磁拓扑理论中重要的BLT方程各个参量的含义及工程应用中的计算方法，并结合一种典型的现代通信网络结构进行了简单的举例分析。电磁拓扑方法在分析现代电子系统对复杂电磁环境的响应中具有重要的理论和工程意义。     

基于丢包的组播网拓扑发现算法研究

由组播网的特点,根据接收节点处丢包的统计,可以推算出组播网络的拓扑结构。文章在组播网络拓扑发现算法BLT的基础上提出了一种基于丢包和跳数的拓扑发现算法HBLT。通过仿真研究表明,HBLT算法比BLT算法有更高的准确性。     

Phase Development and Electrical Properties of Pb(Yb 1/2 Nb 1/2 )O 3 -PbTiO 3 Epitaxial Films

The growth and electrical properties of Pb(Yb 1/2 Nb 1/2 )O 3 -PbTiO 3 (PYbN-PT) epitaxial films were investigated. PYbN-PT epitaxial films with SrRuO 3 bottom electrodes were grown by pulsed laser deposition. Optimization of the growth conditions for the PYbN-PT epitaxial films was carried out on (100) SrRuO 3 /(100) LaAlO 3 substrates using the (50/50) composition target. It was found that formation of pyrochlore phase could be caused not only by low growth temperatures or lead deficiency, but also by poor surface condition of the SrRuO 3 bottom electrodes. (001) PYbN-PT epitaxial films with good crystalline quality were obtained for a range of deposition rates (60-100 nm/min) and temperatures (620-680 °C) after vacuum annealing the SrRuO 3 bottom electrodes. The ferroelectric and piezoelectric properties of 1 w m-thick PYbN-PT epitaxial films with (50/50) and (60/40) compositions and with (001) and (111) orientations were investigated using (100) LaAlO 3 , (100) SrTiO 3 , and (111) SrTiO 3 substrates with SrRuO 3 bottom electrodes. The highest remanent polarization (29 w C/cm 2 ) and effective piezoelectric coefficient e 31.f ( m 14 C/m 2 ) were observed in the (001) PYbN-PT (50/50) film. The transition temperature of the (001) PYbN-PT (50/50) film was about 380 °C. Because of the degradation of the target during the deposition, a 3 w m-thick film was prepared by three depositions (1 w m each layer). The 3 w m-thick film exhibited a higher e 31.f coefficient of m 19 C/m 2.     

基于BLT方程的电磁干扰建模

为了解决场线耦合下传输线负载端响应问题,基于BLT方程建模思想,利用电磁拓扑概念中的管道和节点概念构建了计算的物理模型;利用场线耦合、传输线理论结合叠加原理推导了线上负载干扰的计算方法;利用辐射场空间传播、传输线散射理论结合叠加原理推导了空间场的计算方法;对节点处的电压方程进行合并、整理得到了类似BLT方程的矩阵方程。计算结果表明,该分析方法不仅可计算传输线负载响应,还可计算空间电磁场。与其它论文计算结果的比较证实其模型、推导、计算的正确性。     

La掺杂对BLT薄膜微观结构与性能的影响

采用sol-gel工艺低温制备了Si基Bi4–xLaxTi3O12(BLT)铁电薄膜。研究了La掺杂量对薄膜微观结构、介电和铁电性能的影响。结果表明,600～650℃退火处理的BLT薄膜表面平整无裂纹,晶粒均匀,无焦绿石相或其它杂相,薄膜为多晶生长;La掺杂量x在0.5～0.85的BLT薄膜介电与铁电性能优良,其εr和tanδ分别介于284～289和(1.57～1.63)×10–2,4V偏压下薄膜的漏电流密度低于10–8A/cm2,Pr可达(13.0～17.5)×10–6C/cm2,Ec低至(102.5～127.8)×103V/cm。     

Fabrication and Characterization of Gate-Connected 1T2C-Type Ferroelectric Memory with Paired Bi4 − xLaxTi3O12 Capacitors

A gate-connected 1T2C-type ferroelectric memory, in which the bottom electrodes of paired ferroelectric capacitors are connected to the gate electrode of an underlying FET (field effect transistor) on the field oxide region, was fabricated using a Bi_{4 ? x}La_xTi₃O₁₂ (BLT) film and its electrical properties were characterized. The I_D-V_G (drain current-gate voltage) characteristics of a FET combined with a single ferroelectric capacitor showed that the paired capacitors had almost the same ferroelectric property. It was found in the readout operation that there existed an optimum voltage to maximize the drain current on/off ratio between datum ‘1’ and datum ‘0,’ and that the maximum ratio was as large as 6 × 10⁴. It was also found that the drain current level remained constant, even if the readout operation was repeatedly conducted. It was concluded from these results that the 1T2C-type memory was successfully fabricated using the proposed process and operated properly.     

贴片焊层厚度对功率器件热可靠性影响的研究

贴片工艺是用粘接剂将芯片贴装到金属引线框架(一般是由铜制成)上的过程.富铅的Pb/Sn/Ag软焊料在功率器件封装贴片工艺中作为粘接剂应用十分广泛.从功率器件整体来看,贴片焊层毫无疑问是影响器件可靠性最重要的因素之一,其不仅具有良好的导电导热性能,而且该焊层能够吸收由于芯片和引线框架之间的热失配而产生的应力应变,保护芯片免于受到机械应力的损伤.基于Darveaux的热疲劳寿命分析模型,利用功率循环加速实验以及有限元方法具体分析了贴片焊层厚度BLT对于功率器件热可靠性的影响.并通过实验与仿真的结果,提出提高功率器件热可靠性的设计原则.     

TiO_2对BLT微波介质陶瓷结构及介电性能的影响

采用传统固相烧结工艺制备了BaO-La2O3-nTiO2(n为3,4,5和6)微波介质陶瓷,研究了该系陶瓷的相组成、微观形貌和微波介电性能之间的关系。结果表明:该系陶瓷具有较优介电性能的主晶相为斜方晶系BaLa2Ti4O12,并且第二相的存在对其介电性能影响明显。烧结体致密性是Q·f及τf的重要影响因素。当n为4时,获得相对较优的介电性能:εr为139.7,Q·f为1239.0GHz和τf达180.0×10–6℃–1。     

投弃式仪器数据传输信道时频响应求解方法

针对传输函数求解船载投弃式仪器信道分布参数模型误差较大的问题, 提出了一种求解其数据传输信道时频响应的方法.时域响应采用时域有限差分(Finite Difference Time Domain, FDTD)法, 求得信道上任意位置的时域响应, 频域响应采用BLT(Baum-Liu-Tesche)方程结合电磁拓扑理论, 对信道的关键节点进行频域分析.最后测试了信道的时频域波形, 并与理论仿真结果进行对比, 结果表明:在仪器的工作频率内, 理论仿真与试验结果一致, 为进一步地研究终端电路的设计及传输方案的改进提供了理论基础.