Bite and unconfirmed failures

Electronic BITE is poor at identifying hardware failure and in present design approaches tends to create the reviled ‘unconfirmed failure’. A different approach to BITE and unconfirmed failure could improve both operational performance and the cost of maintenance.     

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.     

Exact probabilistic testability measures for multi-output circuits

The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the X-gate, and applying to the resulting graph the analysis based on supergates.     

采用动态邻域扩展算法的非一致CA低功耗确定TPG

针对确定内建自测试向量发生器设计中常存在着对冗余向量依赖,导致测试应用时间增长,并产生额外的测试功耗等问题,提出一种新的低功耗确定测试向量发生器的综合算法.该向量发生器采用非一致细胞自动机的结构实现,利用基于模拟退火的动态邻域扩展算法寻找优化的细胞自动机的拓扑连接关系.对标准组合电路仿真实验的结果表明,所综合出的向量发生器可有效地产生给定的低功耗确定向量集,并且不影响原有的故障覆盖率和测试时间.     

Comments on “Aliasing Properties of Circular MISRs”

The analysis of aliasing probability presented in a recent article, Aliasing Properties of Circular MISRs [1], is based on an error model that cannot adequately represent real circuits. We show why conclusions presented in [1] should not be used in practice, substantiating our claim with experimental results.This work was supported in part by grants from the Natural Sciences and Engineering Research Council of Canada and in part by the British Columbia Advanced Systems Institute     

基于树形解压缩器的低测试数据量方法

提出一种由异或门按照完全二叉树形状排列而成的树形向量解压缩器。该解压缩器的少数输出端需要由大部分的输入端来确定,而且该结构对其输出值的确定关系类似于扫描链中确定位的分布概率,可有效降低测试数据量。实验结果表明,对于ISCAS’89基准电路,该结构最高将测试数据量压缩了77倍。     

内建自测试中多输入特征寄存器的硬件开销的减少

在内建自测试中,针对随机向量测试,本文提出了一种通过输出信号分组压缩来减少多输入特征寄存器MISR的硬件开销的方法。该方法是在分析输出信号之间相关性的基础上,根据给定的MISR阶数构造具有最小相关度的输出信号集合组,以此来减少输出信号分组压缩时的故障覆盖率损失。该方法不需附加任何辅助电路。     

一种相对游程长度编码方案

提出一种相对游程长度编码方案,以在不增加待编码数据中游程数量的情况下,达到减少待编码游程长度的目的,即通过缩短代码字长度来提高压缩效果。对ISCAS89部分基准电路的实验结果显示,提出的方案在压缩效率和解压结构方面都明显优于Golomb码、FDR码、EFDR等同类方案。     

一种新颖的乘法器核内建自测试设计方法

提出一种新颖的乘法器核内建自测试（BIST）方法。结合C可测性与伪随机测试的优点。所设计的测试电路的附加面积比传统的伪随机电路要低56％，该方法采用独特的赋值方法。生成精简的、故障覆盖率高于99％的测试图形，并用开发的软件对测试图形排序和压缩，平均跳变密度和宽度得以大大减少．基于上述研究成果，可容易实现低成本BIST电路，基于Synopsys相关工具软件的模拟和分析结果表明，提出的BIST电路在面积、功耗和速度等方面均优于现有的BIST设计。     

基于旋转坐标系IPMSM的容错控制策略研究

针对内置式永磁同步电机(IPMSM),当以旋转变压器为位置传感器发生严重故障时,提出了一种故障诊断及容错的方案。采用了基于旋转坐标系的改进滑模观测器算法和TypeⅡ型跟踪环路转子位置和角速度提取算法,用于IPMSNM的转子位置和角速度的估算。利用估算数据分析并检测位置传感器是否出现故障,并采用加权算法实现故障情况下系统的平滑切换。通过搭建MATLAB/Simulink仿真模型对设计的方案进行验证,输出的结果显示了此方案具有较好的容错控制效果,说明了提出的这个方案可行性和有效性。