Novel reagents for iron and sulphur control in medium temperature leaching of sulphide concentrates

Hydrometallurgical leaching of sulphide concentrates of copper and nickel at medium temperature (150°C) produces residues that contain sulphur and iron-bearing minerals and phases. During leaching, and depending on various process parameters, iron may be precipitated as hematite, goethite, jarosite or other oxyhydroxides, which may be more or less crystalline. Hematite is the favoured iron precipitate, because it is the most environmentally stable and does not ad/absorb as much copper, nickel or other solution constituents during precipitation. However, the low solubility of iron during the medium temperature processing of sulphide ores can favour the formation of poorly crystalline, nano-scale iron oxide/oxyhydroxide phases. In some cases, these phases have been positively identified as the metastable ferrihydrite, which transforms into iron oxides such as goethite, hematite and magnetite over time. A better understanding of what may help drive this transformation during leaching would ultimately result in lower valuable metal losses and more stable leach residues. Higher acid concentrations result in increased copper extractions and favour the formation of hematite during concentrate leaching, rather than other metastable phases. Furthermore, commercially available water displacement formula ‘WD40®’ and other novel reagent(s) affect Fe precipitation and sulphur chemistry, leading to very different process outcomes such as improved extractions and larger, more easily separated, sulphur particles.     

应力技术改善CMOS器件性能研究进展

随着集成电路技术的快速发展,等比例缩小技术已经不能满足摩尔定律,应变硅金属氧化物硅场效应晶体管(MOSFET)技术成为后硅时代研究的热点。应变硅技术通过拉伸或压缩硅晶格达到器件尺寸不变的情况下,可提高器件性能的目的,同时应变硅技术与传统硅工艺兼容,节约了生产成本。对于应变硅互补金属氧化物硅晶体管(CMOS)器件的性能以及可靠性问题的研究也日益增加。本文通过介绍几种常用的应变技术(应力记忆技术(SMT),锗化硅技术(SiGe),接触孔刻蚀阻挡层(CESL))的应变机理、材料性能和工艺条件对应力技术的影响来探讨以后应力技术的发展趋势。     

Comprehensive effects of strained Ge1−xSnx and device layout arrangement on a nano-scale Ge-based PMOSFET with a short channel

Layout patterns, including salient gate width and dummy active diffusion region (dummy OD), significantly influence the carrier mobility gain of nano scale devices. Germanium (Ge)-based devices with Ge–tin (GeSn) alloy embedded in the source/drain (S/D) regions have been regarded a promising candidate for higher channel mobility. Second-order piezoresistance coefficients were used to estimate the carrier mobility gain within the desired Ge-based device channel. A 20 nm Ge-based p-type metal oxide semiconductor field effect transistor with 100 nm gate width and 100 nm dummy OD width was selected to explore the layout effect of the short channel device. The device consisted of S/D region Ge_1−xSn_x alloy, compressive-stressed contact etch stop layer, and deposited shallow trench isolation with different process-induced stress magnitudes. Maximum carrier mobility gain of 93.65% was obtained when a 10 nm narrow distance between OD and dummy OD was achieved.     

基于槽形结构的c-CESL应变95nm栅NMOSFET性能增强技术

本文针对应变NMOSFET提出了一种基于槽型结构的应力调制技术。该技术可以利用压应变的CESL（刻蚀阻挡层）来提升Si基NMOSFET的电学性能,而传统的CESL应变NMOSFET通常采用张应变CESL作为应力源。为研究该槽型结构对典型器件电学性能的影响,针对95 nm栅长应变NMOSFET进行了仿真。计算结果表明,当CESL应力为-2.5 GPa时,该槽型结构使沟道应变状态从对NMOSFET不利的压应变（-333 MPa）转变为有利的张应变（256 MPa）,从而使器件的输出电流和跨导均得到提升。该技术具有在应变CMOS中得到应用的潜力,提供了一种不同于双应力线（DSL）技术的新方案。     

Interaction influence of S/D GeSi lattice mismatch and stress gradient of CESL on nano-scaled strained nMOSFETs

The intrinsic stress of thin films has become an important resource as advanced strain engineering is introduced into nanoscaled semiconductor devices. The performance of preferred device infrastructure can be studied by estimating stress-induced mobility gain. However, traditional simulation approaches for device stress typically do not consider the eventual consequence of the stress gradient of strained thin films on nanoscaled transistor stress prediction. Thus, the actual operating characteristic of concerned devices can be easily misunderstood. To resolve this issue, this research presents a fabrication-oriented simulation methodology for device stress and combines it with a multi-layered deposition model for thin film. This study aims to explore stress-induced effects on the performance of a Ge-based testing vehicle for 20 nm n-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) with Ge_1−xSi_x alloys embedded into the source/drain regions of the device. Intrinsic stress is introduced via a 1.0 GPa tensile contact etch stop layer (CESL). Analysis results indicate that stress contours adjacent to the top of the device gate are different from those obtained using the conventional simulation method. Moreover, greater CESL stress passes through the spacer and reaches the device channel. Furthermore, a relationship between the stress components and piezoresistivity coefficients of the Ge material is adopted to estimate the width dependence of the Ge-based nMOSFET on its mobility gain. A maximum mobility gain of up to 60.87% is acquired from the estimated results, and a channel width of 200 nm is preserved.     

Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET

This study investigates the effects of oxide traps induced by SOI of various thicknesses (T_SOI = 50, 70 and 90 nm) on the device performance and gate oxide TDDB reliability of Ni fully silicide metal-gate strained SOI MOSFETs capped with different stressed SiN contact-etch-stop-layer (CESL). The effects of different stress CESLs on the gate leakage currents of the SOI MOSFET devices are also investigated. For devices with high stress (either tensile or compressive) CESL, thinner T_SOI devices have a smaller net remaining stress in gate oxide film than thicker T_SOI devices, and thus possess a smaller bulk oxide trap (N_BOT) and reveal a superior gate oxide reliability. On the other hand, the thicker T_SOI devices show a superior driving capability, but it reveals an inferior gate oxide reliability as well as a larger gate leakage current. From low frequency noise (LFN) analysis, we found that thicker T_SOI device has a higher bulk oxide trap (N_BOT) density, which is induced by larger strain in the gate oxide film and is mainly responsible for the inferior gate oxide reliability. Presumably, the gate oxide film is bended up and down for the p- and nMOSFETs, respectively, by the net stress in thicker T_SOI devices in this CESL strain technology. In addition, the bending extent of gate oxide film of nMOSFETs is larger than that of pMOSFETs due to the larger net stress in gate oxide film resulting from additional compressive stress of shallow trench isolation (STI) pressed on SOI. Therefore, an appropriate SOI thickness design is the key factor to achieve superior device performance and reliability.