基于CISC/RISC混合架构的嵌入式MCU设计

CISC与RISC是目前微控制器（MCU）设计的两种主要指令体系。从MCU的架构原理入手分析基于这两种指令体系的MCU的各自功能特点,说明对于不同应用系统所需的嵌入式MCU设计所要考虑的基本问题及关键模块的设计方法。最后,以一款自主设计的八位MCU与CISC型微控制器MCS51、RISC型微控制器PIC16C54的性能作比较,说明基于CISC/RISC混合架构的MCU的一些性能优势。     

X86结构中微程序ROM的实现技术浅析

微程序控制是X86结构的一个显著特点,深入剖析了X86结构中微程序部件的结构形式,对微程序ROM的结构组织、具体电路的实现形式等问题进行了较为详尽的阐述。     

一种兼容微处理器指令译码单元的优化设计

针对与X86微处理器兼容的32位微处理器，研究设计了一种指令译码器。X86指令集结构复杂，串行译码方式实现简单，效率不高。本文在没有更改处理器体系结构的基础之上，把译码过程分成两个步骤，用多个译码部件实现并行译码．并简要证明方案的可行性。最后用VHDL硬件描述语言实现了设计思想，能够单拍译出一条不带前缀的指令，提高了译码效率。     

CISC与RISC结构CPU间软件移植技术问题分析

通过实例对CISC与RISC两种结构CPU在软件移植时遇到的较典型的具有普遍性的全局性资源之———全局变量的应用与保护问题,进行了较详细的分析。在找到问题症结的同时．针对不同实际情况,给出两种正确的解决该问题的方法。     

32位CISC微处理器流水线的设计

介绍一款全正向自主设计的32位CISC结构微处理器龙腾C2中的流水线设计．该处理器与Intel486DX4指令集兼容。针对CISC结构微处理器流水线设计的难点,采用了微指令流水执行等技术．设计了龙腾C2的7级流水线结构。分析了影响流水线正常执行的各种因素,设计了流水线相关处理机制和精确中断实现机制．实现了一个具有较高性能的CISC微处理器的流水线。仿真和综合的结果表明。该流水线的设计满足龙腾C2微处理器的功能和性能要求。     

8位CISC微处理器的设计与实现

介绍了一种基于FPGA芯片的8位CISC微处理器系统,该系统借助VHDL语言的自顶向下的模块化设计方法,设计了一台具有数据传送、算逻运算、程序控制和输入输出4种功能的30条指令的系统。在QUARTUSII系统上仿真成功,结果表明该微处理器系统可以运行在100 MHz时钟工作频率下,能快速准确地完成各种指令组成的程序。     

浅析计算机体系结构和RISC技术

该文系统概述了现代计算机的两种主要体系结构CISC体系和RISC体系,叙述了当代RISC主流技术及主要特征,以及发展趋势,展望了未来计算机体系发展方向。     

A Machine State Transition Approach to Instruction Retargeting for Embedded Microprocessors

This paper presents an interesting approach to retargeting existing software at the assembly (or binary) level from one instruction set to another instruction set. The approach is based on abstracting the instruction set behaviors as symbolic transitions of the machine states. The retargeting process is modeled as a planning process, an AI technique, that finds a plan (a sequence of operations) which brings the target processor from the same initial state to the same final state as the original software does on the source processor. The approach has been successfully applied in a design project of an x86 compatible microprocessor with an embedded internal RISC core for efficient execution. The proposed approach produced optimal x86-to-RISC mapping. In addition, the approach made it easy to keep up with microarchitecture revision during the design exploration phase since the mapping table can be automatically re-generated and re-evaluated promptly, which is difficult to achieve manually.     

The Misprediction Recovery Cache

In modern processors, deep pipelines couple with superscalar techniques to allow each pipe stage to process multiple instructions. When such a pipe must be flushed and refilled, as when predicted program flow beyond a branch is subsequently recognized as wrong, the temporary performance loss is significant. While modern branch target buffer (BTB) technology makes this flush/refill penalty fairly rare, the penalty that accrues from the remaining branch mispredictions is a serious impediment to even higher processor performance. Advanced mechanisms that can reduce this residual misprediction penalty can be of enormous value in future microprocessor designs. In this paper we describe the design and performance of a promising new mechanism called the Misprediction Recovery Cache (MRC). The key results of our study are. (1) Small, finite sized MRCs (16 to 256 entry) can effectively reduce branch penalty in deeply pipelined processors. (2) Commercial Benchmarks such as the Winstone benchmarks make better use of larger M RCs due to large number of unique branch instructions unlike the predominantly technical SPECint benchmarks. (3) The MRC hit rates increase with increasing BTB prediction accuracy (5-200% depending on MRC size) due to fewer residual mispredictions associated with better prediction. (4) For the processor architecture we studied, the M RC resulted in up to 20% improvement in cpi(cycles per instruction). (5) The incremental performance gain achievable by adding an MRC to a modern CISC processor (which uses a BTB with a two-level predictor) is two to three times of what was achievable by going from a one-level predictor to a two-level predictor.     

一种低成本八位嵌入式MCU内核设计

本文介绍了一个低成本大的8位嵌入式微控制器内核设计，设计采用哈佛结构，双数据总线，指令系统兼容CYASM指令集。本文针对减小面积以实现低成本的目的，详细介绍了系统结构及各模块的设计思想和改进方法。