双极型电压比较器的强电磁脉冲效应

基于大电流注入法(BCI),利用瞬态脉冲产生器模拟强电磁脉冲在双极型电压比较器中产生的耦合电流,观测到输出信号在注入瞬态大电流后的波形变化,包括占空比变化及脉冲衍生等。从基本电路原理方面分析了实验现象的产生机理,以及注入电流幅值、电路偏置等因素对双极型电压比较器强电磁脉冲效应的影响。     

输液器温控装置中用2051单片机实现A/D转换

由于单片机所处理的信号是数字信号,对模拟电压信号进行检测处理时首先要用A/D转换器件对其进行A/D转换,然后再进行处理.本论文利用89C2051系列单片机内部独特的结构,不用A/D转换器件即可实现A/D转换,尽可能地降低成本和简化电路结构,并对其测量范围及转换精度进行分析和讨论.     

适用于纹波控制型DC-DC控制器的比较器设计

设计一种适用于纹波控制（Output-Ripple-Based Control）的Buck型DC-DC控制器的比较器,根据PSIM搭建的仿真模型,分析主环比较器性能对系统的影响,设计具有三级预放大的高增益,低延时,低失调电压的比较器电路,采用两种温度系数的电流补偿比较器增益,稳定增益,采用0.5umBiCOMS工艺进行仿真验证,下降沿延时27ns,增益123dB,随温度最大增益变化3.2%,失调电压90uV,达到系统要求。     

一种5位10 GHz SiGe BiCMOS比较器

SiGe BiCMOS提供了性能极其优异的异质结晶体管(HBT),其ft超过70 GHz,β>120,并具有高线性、低噪声等特点,非常适合高频领域的应用。基于SiGe BiCMOS工艺,提出了一种高性能全差分超高速比较器。该电路由宽带宽前置放大器和改进的主从式锁存器组成,采用3.3 V单电压源,比较时钟超过10 GHz,差模信号电压输入量程为0.8 V,输出差模电压0.4 V,输入失调电压约2.5 mV;工作时钟10 GHz时,用于闪烁式A/D转换器可以达到5位的精度。     

逐次逼近A/D转换器综述

从逐次逼近A／D转换器（SA-A／D）的工作原理出发，分别对其核心模块D／A转换器和比较器进行了讨论。SA-A／D转换器中的D／A转换器可分为电压定标、电流定标和电荷定标三种，重点分析了三种目前应用较多的并行电容、分段电容和RC混合结构。SA-A／D转换器中的比较器可分为运放结构比较器和锁存（latch）比较器，实际常常使用这两种结构级联的高速高精度比较器，并配合失调校准技术，达到较高精度。最后，简要总结了SA-A／D转换器的研究现状，阐述了其在精度、速度和功耗三个方面的发展状况。     

介绍一种应用在反舰导弹上的安全自毁装置

本文介绍了一种用于反舰导弹上的全电子式安全自毁装置的设计思想、作用原理和具体线路.该装置利用自动驾驶仪的偏航角信号和方向舵偏角信号作为自毁比较条件.在飞行过程中,由于某种原因导弹偏离预定的航向时,自动驾驶仪输出偏航角和方向舵偏角信号。当其中任一信号大于比较阈值时,比较放大器工作,驱动延时电路,进而输出自毁指令和自毁信号,控制导弹在确定的区域内安全自毁,从而确保试验区域的安全。     

A single-input dual-output 13.56 MHz CMOS AC–DC converter with comparator-driven rectifiers for implantable devices

A highly efficient single-input, dual-output AC–DC converter for wireless power transfer in implantable devices is implemented using the 0.18-µm CMOS process. The proposed AC–DC converter, consisting of three rectifiers with cross-coupled NMOS transistors and comparator-driven PMOS transistors, achieves up to 79.5% power conversion efficiency at 13.56 MHz operation frequency in order to provide dual outputs of 1.2 V and 2.2 V DC voltages along with 6.2 mA and 22.6 mA of current, respectively, to the implant device from a single RF input. The designed IC consumes a core die area of 0.18 mm².     

一种CMOS锯齿波振荡电路的设计

以比较器为核心电路,并采用恒流源充放电技术,设计了一种基于1.2 μmCMOS工艺的锯齿波振荡电路.并利用Cadence SpectreS仿真工具对电路进行了仿真模拟,结果表明,锯齿波信号的线性度较好,同时其信号振荡频率随电源电压的变化和温度的变化很小,性能良好,可广泛应用在PWM等各种电子电路中.     

Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC

This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents I_on more than double, while the off-state currents I_off remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher I_on increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design.