一种基于组合外密钥和明文的离散混沌密码算法

利用混沌信号的特性提出了一种新的对称密钥块加密算法。该算法具有如下特点,不直接使用混沌系统参数和初始条件作为密钥,而这些参数由外部密钥和明文字符通过位置加权运算得到,且外部密钥由长度可变的字符串和一正整数组合,密钥空间很大。明文的每一块加密都依赖于密钥和整个明文。仿真结果表明,密文对明文或初始密钥的任何微小变化均有强烈敏感性;密文分布均匀。故该密码系统具有强壮的抵抗攻击的能力。     

A new approach for low voltage ride through capability in DFIG based wind farm

Protection against voltage dips is very important for transient stability in a Doubly Fed Induction Generator (DFIG). Conventional crowbar circuits have been used for protection of DFIGs; however, they may be insufficient in some transient situations. Therefore, the Low Voltage Ride Through (LVRT) capability was enhanced by a Demagnetization Current Controller (DCC) for the purpose of transient analysis. In addition, both stator and rotor circuit electromotive forces were modeled in a DFIG. The performances of the DFIG models with and without the DCC were compared. Modeling was carried out in a MATLAB/SIMULINK environment. A comparison of system behaviors was made between three-phase faults with and without a stator–rotor dynamic. Parameters for the DFIG including output voltage, speed, electrical torque variations and d–q axis rotor–stator current variations in addition to a 34.5 kV bus voltage were examined. It was found that in the DFIG model the system became stable in a short time when using the DCC.     

DCC／DMAP 催化制备乙酰阿魏酸乙酯

以4－羟基－3－甲氧基苯甲醛为起始原料，合成了中间产物乙酰阿魏酸，再以N，N－二环己基碳二亚胺（ DCC）和4－二甲胺基吡啶（ DMAP）为催化剂，通过酯化反应制备了乙酰阿魏酸乙酯，各步产物通过红外光谱、质谱和元素分析对其结构进行表征确认。实验结果表明：在室温下，催化剂用量为乙酰阿魏酸用量的3％，反应时间为4 h的条件下，产率达到75％，为最优条件。     

降低催化裂化干气的几点措施

介绍了影响催化裂化装置干气产率的原因,分析总结了国内外炼厂为降低催化干气产率而采取的几种技术措施。     

CHP-Ⅰ型裂解催化剂的研制

开发的以较小孔径和较高硅铝比的五元环族分子筛为活性组分的 CHP—1型裂解催化剂,用于大庆蜡油或大港直馏柴油的催化裂解制取低碳烯烃具有优良的水热稳定性、优越的低碳烯烃选择性及较高的低碳烯烃产率。从小试到工业试生产证实催化剂制备工艺可行,重复性好,催化剂物化性能亦能满足流化床操作要求。     

基于DCC+OSPF协议的光网络组网技术研究

提出了一种基于DCC+OSPF协议的光网络组网技术方案,分析了该方案的关键技术并给出了实现方法,最后对该组网技术进行了验证,试验结果表明该技术方案是正确可行的。     

Modeling and Full Decoupling Control of a Grid-Connected Five-Level Diode-Clamped Converter

This paper presents a novel approach to deal with the regulation of the dc-link capacitor voltages and ac-side currents in a grid-connected five-level diode-clamped converter. Due to the controllability problems of this topology, guaranteeing a solid current control and, mainly, a correct dc-link voltage sharing, represents a complex technical challenge. With the purpose of coping with it, an averaged model that describes the system dynamics at both sides of the converter is presented, assuming that a modulation strategy is integrated in the system to generate the switching sequence. In order to derive the proposed model, no restriction concerning the use of only the three nearest vectors to the desired voltage reference is taken into account. Then, several changes of variables are carried out in the model equations to obtain control input decoupling for control purposes, while reducing the complexity of the model as well. Finally, the voltage and current controllers are designed separately using different control inputs in a straightforward way. Neither auxiliary hardware nor complicated mathematical calculations are required to achieve the control objectives. The effectiveness and good performance of the system under the proposed control approach are validated by simulation results, suggesting that the five-level diode-clamped converter can be a solid solution as an interfacing system connected to the utility grid for, e.g., industrial drives or renewable energy applications.     

Gas-cooled reactor thermal hydraulic analyses with MELCOR

Pursuant to the Energy Policy Act of 2005, the High Temperature Gas-Cooled Reactor (HTGR) has been selected as the reference design for the Next Generation Nuclear Plant (NGNP). Stemming from a U.S. Nuclear Regulatory Commission (NRC) HTGR research initiative, a need was identified for validation of systems-level computer code modeling capabilities in anticipation of the eventual need to perform licensing analyses. Because the NRC has used MELCOR for light water reactors (LWR) in the past and because MELCOR was recently updated to include gas-cooled reactor (GCR) physics models, MELCOR is among the system codes of interest to the NRC. This paper describes MELCOR modeling of the General Atomics' Modular High Temperature Gas-Cooled Reactor (MHTGR). The MHGTR is a suitable design for demonstration of MELCOR GCR modeling competency for two reasons: 1) the MHTGR is a predecessor to the more advanced General Atomics’ Gas-Turbine Modular High Temperature Reactor (GTMHR), and 2) experimental data useful for benchmark calculations may soon become available. Using the most complete literature references available for the MHTGR design, researchers at Texas A&M University (TAMU) constructed a MELCOR input deck for the MHTGR to partially validate MELCOR GCR modeling capabilities. Normal and off-normal system operating conditions were modeled with appropriate boundary and initial conditions. MELCOR predictions of system response were obtained for steady-state, pressurized conduction cool-down (PCC), and depressurized conduction cool-down (DCC) scenarios. Code results were checked against nominal MHTGR design parameters, physical intuition, and anticipated GCR thermal hydraulic response. No inherent deficiencies in MELCOR modeling capability were observed, suggesting that the newly-implemented GCR models are adequate for systems-level analysis. If and when experimental benchmark data becomes available, further validation activities may proceed given the modeling efforts discussed herein.     

NURBS曲线插补技术在CNC中的应用

为了提高数控机床的加工精度和效率,在分析传统机床加工轮廓控制方案不足的基础上,提出了一种改进的NURBS曲线插补算法,该算法实现了基于S型速度曲线的加减速控制,并提出时间顺延法,加减速对称法等方法,合理解决了加减速点的预测问题,实现了在线实时自适应的加减速控制。     

Dose control circuit for digital electrostatic electron-beam array lithography

This paper demonstrates a technique for controlling the electron emission of an array of field emitting vertically aligned carbon nanofibers (VACNFs). An array of carbon nanofibers (CNF) is to be used as the source of electron beams for lithography purposes. This tool is intended to replace the mask in the conventional photolithography process by controlling their charge emission using the “Dose Control Circuitry” (DCC). The large variation in the charge emitted between CNFs grown in identical conditions forced the controller design to be based on fixed dose rather than on fixed time. Compact digital control logic has been designed for controlling the operation of DCC. This system has been implemented in a 0.5 μm CMOS process. Chandra Sekhar A. Durisety received his B.E. (Hons.) Instrumentation from Birla Institute of Technology and Sciences, Pilani, India in 1997 and his M.S in Electrical Engineering from University of Tennessee, Knoxville in 2002. Since 2003, he has been working towards his Ph.D degree also in Electrical Engineering at Integrated Circuits and Systems Lab (ICASL), University of Tennessee, Knoxville. He joined Wipro Infotech Ltd, Global R & D, Bangalore, India in 1997, where he designed FPGA based IPs for network routers. Since 1999, he was involved in the PCI bridge implementation at CMOS chips Inc, Santa Clara, CA, and the test bench development for Sony’s MP3 player, while at Toshiba America Electronic Components Inc., San Jose, CA. His research interests include multi-stage amplifiers, data converters, circuits in SOI and Floating Gate Devices. Rajagopal Vijayaraghavan received the B.E degree in electronics and communication engineering from Madras University in 1998 and the M.S degree in electrical engineering from the University of Texas, Dallas in 2001.He is currently working towards the Ph.D degree in electrical engineering at the University of Tennessee. His research interest is in the area of CMOS Analog and RF IC design. His current research focuses on LNAs and VCOs using SOI based MESFET devices. Lakshmipriya Seshan was born in Trivandrum, India on April 30, 1979. She received her B.tech in Electronincs & Communication Engg from Kerala University, India in June 2000 and M.S in Electrical Engg from University of Tennessee in 2004. In 2004, she joined Intel Corporation as an Analog Engineer, where she is engaged in the design of low power, high speed analog circuits for various I/O interface topologies. Syed K. Islam received his B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (BUET) and M.S. and Ph.D. in Electrical and Systems Engineering from the University of Connecticut. He is presently an Associate Professor in the Department of Electrical and Computer Engineering at the University of Tennessee, Knoxville. Dr. Islam is leading the research efforts of the Analog VLSI and Devices Laboratory at the University of Tennessee. His research interests are design, modeling and fabrication of microelectronic/optoelectronic devices, molecular scale electronics and nanotechnology, biomicroelectronics and monolithic sensors. Dr. Islam has numerous publications in technical journals and conference proceedings in the areas of semiconductors devices and circuits. Benjamin J. Blalock received his B.S. degree in electrical engineering from The University of Tennessee, Knoxville, in 1991 and the M.S. and Ph.D. degrees, also in electrical engineering, from the Georgia Institute of Technology, Atlanta, in 1993 and 1996 respectively. He is currently an Assistant Professor in the Department of Electrical and Computer Engineering at The University of Tennessee where he directs the Integrated Circuits and Systems Laboratory (ICASL). His research focus there includes analog IC design for extreme environments (both wide temperature and radiation immune), multi-gate transistors and circuits on SOI, body-driven circuit techniques for ultra low-voltage analog, mixed-signal/mixed-voltage circuit design for systems-on-a-chip, and bio-microelectronics. Dr. Blalock has co-authored over 60 published refereed papers. He has also worked as an analog IC design consultant for Cypress Semiconductor Corp. and Concorde Microsystems Inc.