基于i860的存储器子系统设计

微处理机系统中的存储器子系统设计对整个系统性能的高低有重要的影响，尤其当微处理器的主频越来越高时。本文结合实际例子，给出了一个基于ｉ８６０处理器（４０ＭＨｚ）的主存设计方案，讨论了实际中需仔细考虑的因素。该设计可为其它高性能ＲＩＳＣ系统设计提供参考。     

基于SoC的嵌入式DRAM存储器内建自测试设计

内建自测试(Built-in Self Test,BIST)是测试片上系统(System on- Chip,SoC)中嵌入式存储器的重要技术;但是,利用BIST技术采用多种算法对嵌入式存储器进行测试仍面临诸多挑战;对此,提出了一种基于SoC的可以带有多种测试算法的嵌入式DRAM存储器BIST设计,所设计的测试电路可以复用状态机的状态,利用循环移位寄存器(Cyclic Shift Register,CSR)产生操作命令,利用地址产生电路产生所需地址;通过对3种BIST电路支持的算法,全速测试,面积开销3个方面的比较,表明提出的嵌入式DRAM存储器BIST设计在测试时间,测试故障覆盖率和测试面积开销等各方面都取得了较好的性能.     

PMSS: A programmable memory system and scheduler for complex memory patterns

HPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. However, applications are getting more complex, with multiple kernels and complex data arrangements, generating overhead while scheduling/managing system resources. Due to this reason all classes of multi threaded machines–minicomputer to supercomputer–require to have efficient hardware scheduler and memory manager that improves the effective bandwidth and latency of the DRAM main memory. This architecture could be a very competitive choice for supercomputing systems that meets the demand of parallelism for HPC benchmarks. In this article, we proposed a Programmable Memory System and Scheduler (PMSS), which provides high speed complex data access pattern to the multi threaded architecture. This proposed PMSS system is implemented and tested on a Xilinx ML505 evaluation FPGA board. The performance of the system is compared with a microprocessor based system that has been integrated with the Xilkernel operating system. Results show that the modified PMSS based multi-accelerator system consumes 50% less hardware resources, 32% less on-chip power and achieves approximately a 19x speedup compared to the MicroBlaze based system.     

基于复杂可编程逻辑器件的DRAM控制器的设计与实现

本文介绍了一种用复杂可编程逻辑器件（CPLD）设计DRAM控制器的设计方法,并采用VHDL语言编程实现。     

基于PCI的微机继电保护测试仪通信控制卡的设计及其WDM驱动程序的实现

微机继电保护测试仪作为一种高速测试装置,要求具有很高的实时性和稳定性.阐述了基于PCI总线的微机继电保护测试仪通信控制卡的硬件结构及实现方法,介绍了WDM驱动程序的特点及PCI通信控制卡驱动程序主要模块的开发,完成了整个系统的整合设计.实际应用表明:该系统有效地完成了各种继保测试试验.     

基于主存访问相关解决等技术的高带宽主存控制器设计

随着现代处理器和缓存技术的发展,当代计算机系统的性能日益受到主存系统的制约,对主存带宽的需求将越来越大。论文提出主存访问相关解决、主存访问动态调度和地址重映射三项技术,利用主存访问自身的特性(局部性)、同步DRAM自身的物理特性(操作的并行性)和二者之间的关系(地址映射),设计了新型、高带宽主存控制器,有效地提高了主存系统的带宽。     

A novel low-latency DRAM based on the bitline-discharge rate

As well known by computer architects, the performance gap between the processor and the memory has been increasing over the years. This causes what is known as the memory wall. In order to alleviate the problem, a novel fast readout scheme is proposed in this article for the single-transistor single-capacitor dynamic random-access memory (1T-1C DRAM) cells. The proposed scheme works in the current domain in which the difference between the discharging rates of the bitline in the cases of ‘1’ and ‘0’ readings is detected. The proposed scheme is analysed quantitatively and compared with the conventional readout scheme. It is verified by simulation adopting the 45 nm CMOS Berkley predictive-technology model (BPTM) and shows 44 and 7.7% reductions in the average read-access and cycle times, respectively, as compared to the conventional readout scheme. It is also shown that the power is saved according to the proposed scheme if the probability of occurrence of ‘0’ storage exceeds 66.7%. This minimum value can be alleviated, however, at the expense of a smaller saving in the average read-access time. The impacts of process variations and technology scaling are also taken into account.     

解决中央处理器运算速度与内存系统性能矛盾的一种方案

中央处理器-存储器集成是解决当前处理器运算速度与传统的存储器系统性能滞后的一种新思路。文章运用一个简单的评价模型和模拟运行,分析了几种处理器-存储器集成的方案。     

用8031，DRAM和高速A/D实现快速数据采集

介绍了一个用８０３１，ＤＲＡＭ和高速Ａ／Ｄ等芯片构成的快速数据采集系统。该系统使Ａ／Ｄ转换的数据不经ＣＰＵ“中转”，而直接存入ＤＲＡＭ中。它具有硬件结构简单、价格低廉、易实现大容量存储等优点。本系统对模拟信号的采集并将采集数据送入存储器的周期为８μｓ。     

A new approach to cell size scaling with a multi-dual cell and a buffer/background programming of unified RAM

New investigations are presented here on a high-density and DRAM-like high-speed non-volatile memory (NVM) application of unified RAM (URAM). For a high-density application of URAM, multiple data storage is demonstrated with a multi-dual cell (MDC). Because each NVM state can be split by programming with a one-transistor (1T) DRAM without a capacitor, the total number of memory states can be doubled. Furthermore, a high-speed DRAM-level NVM scheme is proposed for the joint operation of 1T DRAM buffer programming and NVM post-background programming. The MDC and the proposed scheme are unique URAM properties that can extend the application range of memory devices.