磁阻旋转变压器等效电路及原边反射误差分析

磁阻式旋转变压器因其结构简单和高可靠性,在新能源汽车主驱电机系统中已有越来越多的应用。在磁阻式旋转变压器的应用中,旋转变压器一般被考虑为一个变比可变的理想变压器,然后根据解码原理,分析解码误差。但是在实际应用中,旋转变压器的励磁、正余弦信号均需通过一定电路进行处理,旋转变压器自身在电路中的实际表现也会引入解码误差,这就需要我们对旋转变压器进行精确的建模,以分析其在电路中的实际负载效应。本文首先介绍了磁阻式旋转变压器的基本原理,然后详细分析了其励磁、信号绕组的自感、互感,并使用励磁绕组、信号绕组的自感、互感导出旋转变压器的等效电路,最后在此等效电路基础上分析旋转变压器与其接入的电路共同引起的解码误差,为旋转变压器的应用电路设计提供依据。     

基于RD26的双通道旋转变压器位置解码设备的设计

双通道旋转变压器的解码问题一直是伺服控制闭环系统非常重要的一个问题,快速、准确的解码出伺服系统位置信息是闭环控制系统的关键。通过对某伺服系统闭环控制系统位置解码技术的研究,分析了RD26的解码过程及原理,设计一种基于RD26的双通道旋转变压器位置解码设备,此设备将双通道旋转变压器输出的信号与RD26相连,通过并口向FPGA发送数据,FPGA通过时序读取RD26信号,能将双通道旋转变压器粗机、精机的模拟电压信号转换成具有绝对位置的数字信号,不需要再进行纠错与粗精结合,解码精度可达到±2角分+1LSB。     

Research on encoding and decoding of non-binary polar codes over GF(2m)

Binary Polar Codes (BPCs) have advantages of high-efficiency and capacity-achieving but suffer from large latency due to the Successive-Cancellation List (SCL) decoding. Non-Binary Polar Codes (NBPCs) have been investigated to obtain the performance gains and reduce latency under the implementation of parallel architectures for multi-bit decoding. However, most of the existing works only focus on the Reed-Solomon matrix-based NBPCs and the probability domain-based non-binary polar decoding, which lack flexible structure and have a large computation amount in the decoding process, while little attention has been paid to general non-binary kernel-based NBPCs and Log-Likelihood Ratio (LLR) based decoding methods. In this paper, we consider a scheme of NBPCs with a general structure over GF(2^m). Specifically, we pursue a detailed Monte-Carlo simulation implementation to determine the construction for proposed NBPCs. For non-binary polar decoding, an SCL decoding based on LLRs is proposed for NBPCs, which can be implemented with non-binary kernels of arbitrary size. Moreover, we propose a Perfect Polarization-Based SCL (PPB-SCL) algorithm based on LLRs to reduce decoding complexity by deriving a new update function of path metric for NBPCs and eliminating the path splitting process at perfect polarized (i.e., highly reliable) positions. Simulation results show that the bit error rate of the proposed NBPCs significantly outperforms that of BPCs. In addition, the proposed PPB-SCL decoding obtains about a 40% complexity reduction of SCL decoding for NBPCs.     

Turbo码交织矩阵的一种改进设计

Ｔｕｒｂｏ码以其优异的性能而迅速成为近年来信道编码领域研究的热点。在Ｔｕｒｂｏ码的设计中,交织矩阵是影响其整体性能的重要因素。尤其是在采用小规模交织矩阵时,不同的设计产生的结果差别很大,本文提出一种交织矩阵的改进设计方法,它能够使成员码编码器网络在一帧数据编码结束后全部终结归零,从而为译码判决提供了正确的初始条件,与传统的非全归零交织矩阵相比较,分析结果表明本文提出的设计方案性能更优。３１     

Android下OpenMax IL框架的研究和应用

由于Android系统多媒体引擎使用的是OpenMax软件解码组件,出现了播放分辨率较高视频不流畅的问题。为此,提出在Android系统上设计一OpenMax硬件解码组件,并将其放在嵌入式开发平台上进行测试。该组件是在对Android系统自带Open-Max IL层进行研究的基础上,以SamSung S3C6410为嵌入式核心处理器,针对MPEG-4视频流而设计。实验结果表明,设计的硬件解码组件优于系统自带的软件解码组件,表明该方案切实可行。     

单片机实现海明码纠错原理的研究

介绍了海明码的编码、解码、纠错原理及其构造方法,并将纠错原理应用于单片机之间的串行通信.阐述了发送机发送程序与接收机接收程序的流程,以及单片机实现海明码软件编码、解码的具体过程,并给出了找出一位差错并进行纠正的方法.该方法用于单片机遥测和遥控系统,具有高性价比、高可靠和操作简便的优点.     

Integrated cost optimization in a two-stage,automotive supply chain

The efficiency of the automotive supply chain is crucial for ensuring the competitiveness of the automotive industry, which represents one of the most significant manufacturing sectors. We model the integrated production and transportation planning problem of a Tier-1 automotive supplier while taking into account realistic conditions such as sequence-dependent setups on multiple injection molding machines operating in parallel, auxiliary resource assignments of overhead cranes, and multiple types of costs. Finished parts go to the integrated supply chain׳s second stage, transportation, for subsequent delivery by capacitated vehicles to multiple distribution centers for meeting predefined due date requirements. We develop a mixed-integer, linear programming model of the problem, and then present a hybrid simulated annealing algorithm (HSAA), including a constructive heuristic. Our proposed HSAA employs an effective encoding-decoding strategy to solve the NP-hard problem to near optimality in a timely manner. Computational results demonstrate the promising performance of the proposed solution approach.     

多元LDPC码列分层DBC译码算法

针对多元LDPC码扩展最小和（Extended Min Sum,EMS）译码算法收敛速度慢、运算复杂度高的问题,提出一种多元LDPC码列分层动态检泡（Dynamic Bubble-Check,DBC）译码算法。首先对变量节点按不同列重进行分层处理,译码时率先更新列重较大分层的变量节点消息,不同层之间采用串行方式进行消息传递,通过并串结合的方式降低译码迭代次数。在校验节点消息更新过程中,采用动态检泡方法减少EMS算法中的运算量,降低算法复杂度。仿真结果表明,在几乎不损失性能的前提下,该算法的平均最大迭代次数仅为EMS译码算法的50%,复杂度降低为EMS算法的50%。     

用于HDTV视频解码器的高性能SDRAM控制器

该文提出了一种适用于HDTV视频解码器的高性能SDRAM控制器。通过为SDRAM控制器设置多个端口并集成仲裁功能,该SDRAM控制器可以取代传统的总线＋DMA结构,为解码器中的功能单元有效地分配存储器的带宽资源。该文提出的SDRAM控制器内建流水线式的地址和数据路径,配合SDRAM本身流水处理指令的特性,能够无延时地处理各个端口上的存储器访问请求,从而降低了对片上缓存的需求。仿真综合结果表明,该文设计的SDRAM控制器满足HDTV解码的性能要求,且与总线＋DMA结构相比,片上缓存容量减少了约70%。     

一种适用于高清视频解码的反离散余弦变换的VLSI实现

提出了一种面向视频处理应用的二维8X8IDCT(反离散余弦变换)处理器结构.该处理器设计利用了IDCT算法中的对称性,采用基于并行的乘累加器的结构加快处理速度.设计过程中对于有限位宽对运算结果误差及精度的影响进行了仿真与分析,并根据要求确定了运算位宽的优化值,在满足精度的条件下使芯片的面积开销最小.该处理器核的面积为48K逻辑门,能够在0.64μs内完成对一个数据块的运算,可以满足对高清晰度视频实时解码的性能需求.