占空比为50%的数控分频器设计及实现

针对FPGA外部时钟信号过高的特点,在分析偶数分频和奇数分频的基础上,采用VHDL设计一种占空比为50%的数控分频器,并在QuartusⅡ环境下进行仿真实验。实验结果表明,设计方案是可行的,具有很强的实用价值。     

适用于ASIC的高速低功耗逻辑单元

本文介绍一种ECL电路结构形式的ASIC逻辑单元的设计和应用。该单元使用2.5V的电源,内部开关电流设计为0.5mA,逻辑摆幅设计为340mV,输入输出均采用双向互补信号。它具有信息的基本记忆功能,用它进行多级组合配套设计,可制作不同模数的分频器、寄存器和计数器等。设计灵活,功能强,电路速度快,功耗低,仅为具有相同功能的普通ECL电路的1/30。这些电路可用在通讯机、电子控制系统、电子测量系结中作高速数字锁相环,数字信号处理的专用集成电路。     

FGMOS based voltage-controlled resistor and its applications

The paper presents floating gate MOSFET (FGMOS) based low-voltage tunable resistor operating at supply voltages of ±0.75 V. The proposed circuit is then used as basic building block to develop tunable negative resistor, current-mode divider, and variable transresistance amplifier. The circuit is simple, compact, and accurate. The total power dissipation of the proposed circuit is 18.6 μW. The circuits are simulated to demonstrate the effectiveness using SPICE in 0.5-μm CMOS technology.     

调频锁相环路中分频器对调频的影响

本文详细分析了调频锁相环路中分频器的作用,给出了选择分频比的依据。     

Modeling of conjugated heat transfer in a thick walled enclosure filled with nanofluid

The objective of this paper is to investigate the conjugated heat transfer in a thick walled cavity filled with copper-water nanofluid. The analysis uses a two-dimensional rectangular enclosure under conjugated convective-conductive heat transfer conditions and considers a range of Rayleigh numbers. The enclosure was subjected to a constant and uniform heat flux at the left thick wall generating a natural convection flow. The thicknesses of the other boundaries are assumed to be zero. The right wall is kept at a low constant temperature while the horizontal walls are assumed to be adiabatic. A moveable divider is located at the bottom wall of the cavity. The governing equations are derived based on the conceptual model in the Cartesian coordinate system. The study has been carried out for the Rayleigh number in the range of 10⁵ ≤ Ra ≤ 10⁸, and for the solid volume fraction at 0 ≤ ? ≤ 0.05. Results are presented in the form of streamlines, isotherms, average Nusselt number and input heat absorption by the nanofluid. The effects of solid volume fraction of nanofluids, the location of the divider and also the value of the ambient convective heat transfer coefficient on the hydrodynamic and thermal characteristics of flow have been analyzed. An increase in the average Nusselt number was found with the solid concentration for the whole range of Rayleigh number. In addition, results show that the position of the divider and the ambient convective heat transfer coefficient have a considerable effect on the heat transfer enhancement.     

光纤激光器的研究与发展

介绍光纤激光器的工作原理、分类以及为消除激射过程中的许多不利因素，提高光束质量而采取的技术措施，同时介绍近几年同内外光纤激光器的研究与发展。     

"空城计"防盗自动开关设计

介绍一种可用于防盗的白炽灯自动开关.利用1只14位二进制串行计数/分频器和振荡器芯片,取其多次分频后的输出信号相与得一方波控制信号,以此信号触发一双向可控硅,控制灯电源自动地时通时断.     

用Verilog HDL实现基于FPGA的通用分频器的设计

在数字逻辑电路设计中,常常遇到一些对时钟分频的需求。本文实现了一种基于FPGA的软件化的分频方法,通过对不同的Verilog HDL语言程序语句进行比较分析和仿真综合。     

比例分流阀的仿真分析与实验研究

提出了一种比例分流阀的结构。通过建模仿真和试验测试,研究进口流量和负载压差对比例分流阀的分流误差的影响。仿真结果与试验结果基本吻合,进口流量、负载压差及其正负值对分流误差的大小均有影响。试验还表明:比例分流阀在实际工作过程中,由于内泄漏、稳态液动力等因素的影响,导致试验的分流误差值较仿真的分流误差值大。     

基于DDS的小数分频器的设计

基于直接数字频率合成器DDS芯片AD9850的小数分频器设计,分频系数N是可以在限定范围内自行设置的任一小数,提出了三种不同计算输入时钟频率值的方法,并给出AD9850并行连接的源代码及实现小数分频器的基本结构框图,并对三个主要模块CPLD/FPGA、DDS（AD9850）和单片机（80C51）之间的连接加以详细的说明。