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Myeong‐Hoon Oh Young Woo Kim Sanghoon Kwak Chi‐Hoon Shin Sung‐Nam Kim 《ETRI Journal》2013,35(3):480-490
As technology evolves into the deep submicron level, synchronous circuit designs based on a single global clock have incurred problems in such areas as timing closure and power consumption. An asynchronous circuit design methodology is one of the strong candidates to solve such problems. To verify the feasibility and efficiency of a large‐scale asynchronous circuit, we design a fully clockless 32‐bit processor. We model the processor using an asynchronous HDL and synthesize it using a tool specialized for asynchronous circuits with a top‐down design approach. In this paper, two microarchitectures, basic and enhanced, are explored. The results from a pre‐layout simulation utilizing 0.13‐μm CMOS technology show that the performance and power consumption of the enhanced microarchitecture are respectively improved by 109% and 30% with respect to the basic architecture. Furthermore, the measured power efficiency is about 238 μW/MHz and is comparable to that of a synchronous counterpart. 相似文献
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针对超临界机组锅炉烟气脱硫(FGD)吸收塔入口烟道的腐蚀特征,提出防腐贴衬材料的选型应以耐蚀性为基础,通过对常用材料腐蚀数据的对比,得出C276系列合金是应用于电厂脱硫系统入口烟道腐蚀环境的首选金属材料,并对常用的哈氏合金C276的焊接工艺进行了分析,指出了需要注意的问题。 相似文献
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